Jetson-tx2 irq affinity support?

Robotics & Edge Computing Jetson & Embedded Systems Jetson TX2
1

Hi:
I want know how to bind gpio irq to specified CPU, my sdk is r32.4

root@nvidia-desktop:/# cat /proc/interrupts
CPU0 CPU1 CPU2 CPU3 CPU4 CPU5
…
338: 34766 0 0 0 0 0 tegra-gpio-aon 21 Edge imu_irq
i want bind imu_irq to other CPU

2

You will probably be interested in “taskset”. See:
https://forums.developer.nvidia.com/t/irq-balancing/126244/6
https://www.kernel.org/doc/Documentation/IRQ-affinity.txt

If you are working with Denver cores, then you might also want to see this:
https://forums.developer.nvidia.com/t/threads-running-on-an-asymmetric-system-parker-soc-has-2-denver-cores-and-four-arm-cortex-a57/126242/5

I don’t know if the particular imu_irq can be set to other cores or not. There are some cases where certain hardware interrupts have to remain on CPU0.

3

Hi:
I found IMU(spi interface) IRQ belong to tegra-gpio-aon type, I can’t change this irq affinity.
but irq-99 (GICv2), I can change irq affinity

root@nvidia-desktop:/proc/irq/338# ls
affinity_hint imu_irq node smp_affinity smp_affinity_list spurious
root@nvidia-desktop:/proc/irq/338# cat smp_affinity
3f

echo 2 > smp_affinity
bash: echo: write error: Input/output error
root@nvidia-desktop:/proc/irq/338# cat /proc/interrupts | grep 338
338: 25799 0 0 0 0 0 tegra-gpio-aon 21 Edge imu_irq

root@nvidia-desktop:/proc/irq/99# cat smp_affinity
02
root@nvidia-desktop:/sys/devices/system/cpu/cpu1# cat /proc/interrupts
CPU0 CPU1 CPU2 CPU3 CPU4 CPU5
99: 5031 16467 0 0 0 0 GICv2 113 Level gpcdma.6

root@nvidia-desktop:/sys/devices/system/cpu/cpu1# cat /proc/interrupts
CPU0 CPU1 CPU2 CPU3 CPU4 CPU5
333: 0 0 0 0 0 0 tegra-gpio-aon 16 Level tmp451
338: 21499 0 0 0 0 0 tegra-gpio-aon 21 Edge imu_irq
373: 0 0 0 0 0 0 tegra-gpio-aon 56 Edge Power
374: 0 0 0 0 0 0 tegra-gpio-aon 57 Edge KEY_VOL+
375: 0 0 0 0 0 0 tegra-gpio-aon 58 Edge KEY_VOL-
377: 0 0 0 0 0 0 tegra-gpio-aon 60 Edge bluetooth hostwake

4

Some hardware IRQs have different wiring, and although I couldn’t tell you which is which, I can tell you that some can only route to the first CPU core due to actual wiring not supporting reprogramming to any other core. If you give your use-case, then someone from NVIDIA might be able to offer suggestions on possibilities and limitations.

5

Hi:
We will use four or more imu on two spi bus in my case, and we need imu irq (use gpio) notify CPU read imu data from IMU fifo. We need to time stamp IMU data in irq handler (top half). So imu irq need High priority and real-time.
It’s found that there is a delay of several milliseconds(about 6ms) from the trigger of hardware interrupt to the call of irq handler

7

hello luopinjing,

affinity can only be set at the GIC level, you may check #cat /proc/interrupts for reference,
how about enable nice commands to configure higher priority for your process?
thanks