Does TX1 PCIe Root support more than one MSI interrupt vector from an End Point? We have an EP in an FPGA connected to TX1 Root PCIe and we enabled 2 MIS interrupts for the FPGA EP to send but when we try to enable and allocate these two in TX1 Linux it return an error saying that only one is available. I have contacted the FPGA manufacturer and they confirmed that they support more that one interrupt and confirmed that my FPGA design and procedure is correct. What should we do to get that working in TX1?
Here is the lspci -x -v output in Linux:
We do support multiple MSIs as we have seen no issues with MSI-X. I’ll try to look for a card with only MSI support and see if there is any issue with that. For time being, if it possible to use MSI-X (given the end point is an FPGA based design), please use it, meanwhile I’ll figure out if there is any issue with MSI only cards.
I am having the exact same problem, also a Xilinx FPGA as the endpoint.
lspci -v
shows the Xilinx PCI device supports 32 MSI interrupts, but calling
pci_enable_msi_block(pdev, 3)
in the Linux driver returns 1.
We are researching whether we can use MSI-X, but I’m wondering if either of you have further information, either @Kben (MSI-X support on Xilinx) or @vidyas (MSI support on Tegra)?
Thanks!
1:00.0 Signal processing controller: Xilinx Corporation EUROCOM for PCI (ECOMP) (rev 01)
Subsystem: Xilinx Corporation EUROCOM for PCI (ECOMP)
Flags: bus master, fast devsel, latency 0, IRQ 643
Memory at 32200000 (32-bit, non-prefetchable)
Capabilities: [40] Power Management version 3
Capabilities: [48] MSI: Enable+ Count=1/32 Maskable- 64bit+
Capabilities: [60] Express Endpoint, MSI 00
Capabilities: [100] Device Serial Number 00-00-00-00-00-00-00-00
Kernel driver in use: pci_xilinx
We found the spot in the kernel driver source code where it limits MSI interrupts to only 1. It seems the platform drivers (Tegra in this case) can override the default routine to support more than one, but nVidia hasn’t done that.
Hopefully we can figure out MSI-X. The alternative is to have all of the ‘interrupts’ generated on the FPGA actually raise just the one interrupt, but then we’d need some sort of dispatcher to determine which ‘function’ is the source of the interrupt and pass it to the proper piece of code.
We have decided to have just one interrupt for all functions on the board. We have added a register in the FPGA that provides an id for the source of the interrupt, and I’ve written an interrupt dispatcher to call the appropriate handler based on that id.
I have the problem about msi interrupt. In pci driver code,I use
“ret = pci_enable_msi(lw->pcidev);
if (ret)
v4l2_err(&lw->v4l2_dev, “MSI not available.\n”);
//request irq
lw->irq = pdev->irq;
printk(“irq nu = %d\n”,lw->irq);
if (request_irq(lw->irq, handl_irq,0, “edw”, (void*)lw)) {
v4l2_err(&lw->v4l2_dev, “request_irq failed\n”);
return (CRIT_ERR);” to request msi interrupt. And I read xilinx FPGA PCIE MSI register with msi_enable_bit = 1.
Use xilinx chipscope, I can see msi message transfer to TX2. But tx2 doen not receive any interrupt.
I use cat/proc/interrupt | grep edw(pcie driver interrupt name),show :
“198: 0 0 0 0 tegra-gpio 65 Edge edw”
I’m confused, why my pcie driver interrupt register to “tegra-gpio” but not “GICv2”?