EP Mode DMA test Fail When USING PEX88096 RDK PCIe switch

HI: I am following the topic The bandwidth of of virtual ethernet over PCIe between two xaviers is low - #19 by WayneWWW. to test RC mode and EP mode DMA function
1 When I connect RC Xavier and EP Xavier directly with Cable,Two Mode (RC & EP) DMA works fine.
2 when connect RC an EP with PEX88096 RDK board as pcie switch ,only RC mode DMA work, EP mod DMA would report an err as below

[  509.480007] t19x-arm-smmu 12000000.iommu: Unhandled context fault: smmu0, iova=0x13fffff000, fsynr=0x240011, cb=3, sid=91(0x5b - PCIE5), pgd=0, pud=0, pmd=0, pte=0
[  509.480657] mc-err: vpr base=0:c6000000, size=20, ctrl=3, override:(a01a8340, fcee10c1, 1, 0)
[  509.480803] mc-err: (255) csw_pcie5w: MC request violates VPR requirements
[  509.480939] mc-err:   status = 0x0ff740e3; addr = 0xffffffff00; hi_adr_reg=008
[  509.481053] mc-err:   secure: yes, access-type: write
[  509.481144] mc-err: mcerr: unknown intr source intstatus = 0x00000000, intstatus_1 = 0x00000000
[  509.481311] mc-err: mcerr: unknown intr source intstatus = 0x00000000, intstatus_1 = 0x00000000
[  514.716349] tegra_ep_mem 0005:0b:00.0: DMA write operation timed out no interrupt
[  514.716526] tegra_ep_mem 0005:0b:00.0: something is wrong in write

The bus topology is shown below:

-+-[0005:00]---00.0-[01-ff]----00.0-[02-20]--+-00.0-[03-1c]----00.0-[04-1c]----10.0-[05-1c]----00.0-[06-1c]--+-00.0-[07-0b]----00.0-[08-0b]--+-00.0-[09]----00.0  Xilinx Corporation Device 9038
|                                           |                                                               |                               +-08.0-[0a]--
|                                           |                                                               |                               \-10.0-[0b]----00.0  NVIDIA Corporation Device 1ad5
|                                           |                                                               +-04.0-[0c-0e]----00.0-[0d-0e]----10.0-[0e]--
|                                           |                                                               +-08.0-[0f-17]----00.0-[10-17]--+-00.0-[11]--
|                                           |                                                               |                               +-04.0-[12]--
|                                           |                                                               |                               +-08.0-[13]--
|                                           |                                                               |                               +-10.0-[14]--
|                                           |                                                               |                               +-14.0-[15]--
|                                           |                                                               |                               +-18.0-[16]--
|                                           |                                                               |                               \-1c.0-[17]--
|                                           |                                                               +-0c.0-[18-1b]----00.0-[19-1b]--+-14.0-[1a]--
|                                           |                                                               |                               \-15.0-[1b]--
|                                           |                                                               \-1c.0-[1c]----00.0  LSI Logic / Symbios Logic Device c010
|                                           +-04.0-[1d-1f]----00.0-[1e-1f]----00.0-[1f]--
|                                           \-1c.0-[20]----00.0  LSI Logic / Symbios Logic Device c010
+-[0001:00]---00.0-[01-ff]----00.0  Marvell Technology Group Ltd. Device 9171
\-[0000:00]-

I’m using jetpcak 4.5.1 Code
What should I do to fix the Err ?

Regards,

Sorry for the late response, we will do the investigate to do the update soon.

Can you please confirm that the PCIe switch in between is not doing any internal buffering and sending upstream transactions at a later point (i.e. after the buffers are unmapped in the host)?
Also, do you observe this only during data transfers or during simple ping as well?

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