Force rescan of PCIe bus?

Autonomous Machines Jetson & Embedded Systems Jetson TX1
#1

Is there a way to force the PCIe bus to re-scan all devices after boot? This is quite useful for developing FPGA based PCIe devices, which are rebooted frequently in dev.

The internet says the proper way is this, but it seems to have no effect on the TX1:

echo 1 > /sys/bus/pci/rescan
#2

I have not tried to rescan, but was your echo command done sudo? If not, then it’d probably fail for lack of permissions.

#3

It is with sudo.

#4

There are couple of ways to handle this (i.e. end point being an FPGA and comes up slowly) situation

  1. There is an entry in device tree “nvidia,boot-detect-delay” which can be used to delay enumeration by a specified time
  2. Make PCIe host controller driver as a loadable module (pci-tegra.ko) and insmod it only after FPGA is ready
  3. If you can tell me the version being used here (L4T 23 / L4T 24.2 Etc…), I can provide a patch with which we can have only root ports getting enumerated (in case end point is not ready) and later ‘rescan’ can be used to rescan the bus and add newly found devices to hierarchy.
#5

The pci module unload/reload is a great suggestion, however, when I change the Tegra PCI controller to a module in menuconfig, the “make modules” step fails with “disable_scx_states [drivers/pci/host/pci-tegra.ko] undefined!”

I am running L4T 24.2 but can upgrade to 24.2.1 if need be. A rescan patch that works with /sys/bus/pci/rescan would be terrific, bringing it in line with other pci controller drivers.

#6

following patch can be used to have only root ports enumerated in the beginning and after making sure that the end point is ready, “echo 1 > /sys/bus/pci/rescan” can be run to add end points to hierarchy.

diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
index 6c070a9..af85890 100644
--- a/drivers/pci/host/pci-tegra.c
+++ b/drivers/pci/host/pci-tegra.c
@@ -2278,6 +2278,11 @@ static void tegra_pcie_check_ports(struct tegra_pcie *pcie)
            continue;
        }
        dev_info(pcie->dev, "link %u down, ignoring\n", port->index);
+       if (port->status == 0){
+           port->status = 1;
+           pcie->num_ports++;
+           continue;
+       }
        tegra_pcie_port_disable(port);
    }
 #if defined(CONFIG_ARCH_TEGRA_21x_SOC)
#7

I tried this change on xavier L4T 32.1, which doesn’t work.