I want to pull up the RST pins of pcie0~pcie2 during power-on initialization on TX2.
But I didn’t find the gpio number of the above pins from DTB.
How should I modify the source code of R32.1？
Thanks in advance!
hello 295839633,
you should modify ODMDATA to configure number of PCIe you would like to use,
please refer to [Jetson TX2 Platform Adaptation and Bring-Up Guide]->[USB Lane Mapping] from Jetson Download Center
thanks
Thank you for replying!
I’ve successfullly configured the number of PCIe as following log:
[ 0.484143] iommu: Adding device 10003000.pcie-controller to group 49
[ 0.484170] arm-smmu: forcing sodev map for 10003000.pcie-controller
[ 0.895091] tegra_pcie_parse_dt: no rst_gpio--------------------------
[ 0.895148] tegra_pcie_parse_dt: no rst_gpio--------------------------
[ 0.895186] tegra_pcie_parse_dt: no rst_gpio--------------------------
[ 0.895218] tegra-pcie 10003000.pcie-controller: 1x1, 1x1, 1x1 configuration
[ 0.896417] tegra-pcie 10003000.pcie-controller: PCIE: Enable power rails
[ 0.896857] tegra-pcie 10003000.pcie-controller: probing port 0, using 1 lanes
[ 0.896891] tegra_pcie_port_get_pex_ctrl: AFI_PEX0_CTRL-----------------------
[ 0.896920] tegra_pcie_port_get_pex_ctrl: AFI_PEX0_CTRL-----------------------
[ 0.900648] tegra-pcie 10003000.pcie-controller: probing port 1, using 1 lanes
[ 0.900692] tegra_pcie_port_get_pex_ctrl: AFI_PEX1_CTRL-----------------------
[ 0.900748] tegra_pcie_port_get_pex_ctrl: AFI_PEX1_CTRL-----------------------
[ 0.902962] tegra-pcie 10003000.pcie-controller: probing port 2, using 1 lanes
[ 0.903015] tegra_pcie_port_get_pex_ctrl: AFI_PEX2_CTRL-----------------------
[ 0.903072] tegra_pcie_port_get_pex_ctrl: AFI_PEX2_CTRL-----------------------
But I want to pull up the two pins-PEX0_RST&PEX2_RST& all the time even if no PCIe device is detected.
Is there any way to maintain the high level of these two pins?
I found the PEX_RST pins be raised by the following code in “pci-tegra.c”:
static void tegra_pcie_port_reset(struct tegra_pcie_port *port)
{
unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
unsigned long value;
PR_FUNC_LINE;
/* pulse reset signal */
/* assert PEX_RST_A */
if (gpio_is_valid(port->rst_gpio)) {
gpio_set_value(port->rst_gpio, 0);
} else {
value = afi_readl(port->pcie, ctrl);
value &= ~AFI_PEX_CTRL_RST;
afi_writel(port->pcie, value, ctrl);
}
usleep_range(1000, 2000);
/* deAssert PEX_RST_A */
if (gpio_is_valid(port->rst_gpio)) {
gpio_set_value(port->rst_gpio, 1);
} else {
value = afi_readl(port->pcie, ctrl);
value |= AFI_PEX_CTRL_RST;
afi_writel(port->pcie, value, ctrl);
}
}
I got the waveform of the PEX_RST pins by oscilloscope and found the pins was were pulled up in turn and then pulled down at the same time. The log is as follow:
[ 0.479032] GPIO line 459 (pcie0_lane2_mux) hogged as output/low
[ 0.487980] iommu: Adding device 10003000.pcie-controller to group 49
[ 0.488074] arm-smmu: forcing sodev map for 10003000.pcie-controller
[ 0.890039] PCIE: tegra_pcie_probe(4818)
[ 0.890072] PCIE: tegra_pcie_read_plat_data(3300)
[ 0.890218] PCIE: tegra_pcie_parse_dt(3402)
[ 0.890329] tegra-pcie 10003000.pcie-controller: 1x1, 1x1, 1x1 configuration
[ 0.890383] PCIE: tegra_pcie_probe_complete(4698)
[ 0.890403] PCIE: tegra_pcie_init(2873)
[ 0.890421] PCIE: tegra_pcie_get_resources(1939)
[ 0.890440] PCIE: tegra_pcie_get_clocks(1302)
[ 0.891503] PCIE: tegra_pcie_enable_regulators(1552)
[ 0.891568] tegra-pcie 10003000.pcie-controller: PCIE: Enable power rails
[ 0.891678] PCIE: tegra_pcie_power_on(1823)
[ 0.891809] PCIE: tegra_pcie_restore_device(1764)
[ 0.891834] PCIE: tegra_pcie_module_power_on(1716)
[ 0.891853] PCIE: tegra_pcie_enable_regulators(1552)
[ 0.891872] PCIE: tegra_pcie_map_resources(1597)
[ 0.891913] PCIE: tegra_pcie_enable_pads(1441)
[ 0.892004] PCIE: tegra_pcie_enable_controller(1484)
[ 0.892076] PCIE: tegra_pcie_enable_msi(3113)
[ 0.892161] PCIE: tegra_pcie_check_ports(2513)
[ 0.892185] tegra-pcie 10003000.pcie-controller: probing port 0, using 1 lanes
[ 0.892213] PCIE: tegra_pcie_port_enable(2036)
[ 0.892233] PCIE: tegra_pcie_port_reset(2006)
[ 0.892251] tegra_pcie_port_reset: no rst_gpio------------------
[ 0.894325] PCIE: tegra_pcie_enable_rp_features(2382)
[ 0.894381] PCIE: tegra_pcie_enable_aer(1043)
[ 0.894434] PCIE: tegra_pcie_apply_sw_war(2224)
[ 0.895960] PCIE: tegra_pcie_prsnt_map_override(1101)
[ 0.895989] tegra-pcie 10003000.pcie-controller: probing port 1, using 1 lanes
[ 0.896018] PCIE: tegra_pcie_port_enable(2036)
[ 0.896038] PCIE: tegra_pcie_port_reset(2006)
[ 0.896057] tegra_pcie_port_reset: no rst_gpio------------------
[ 0.898125] PCIE: tegra_pcie_enable_rp_features(2382)
[ 0.898178] PCIE: tegra_pcie_enable_aer(1043)
[ 0.898202] PCIE: tegra_pcie_apply_sw_war(2224)
[ 0.898400] PCIE: tegra_pcie_prsnt_map_override(1101)
[ 0.898427] tegra-pcie 10003000.pcie-controller: probing port 2, using 1 lanes
[ 0.898454] PCIE: tegra_pcie_port_enable(2036)
[ 0.898475] PCIE: tegra_pcie_port_reset(2006)
[ 0.898493] tegra_pcie_port_reset: no rst_gpio------------------
[ 0.899578] PCIE: tegra_pcie_enable_rp_features(2382)
[ 0.899616] PCIE: tegra_pcie_enable_aer(1043)
[ 0.899640] PCIE: tegra_pcie_apply_sw_war(2224)
[ 0.900591] PCIE: tegra_pcie_prsnt_map_override(1101)
[ 0.921834] PCIE: tegra_pcie_port_check_link(2172)
[ 1.325846] tegra-pcie 10003000.pcie-controller: link 0 down, retrying
[ 1.325851] PCIE: tegra_pcie_port_reset(2006)
[ 1.325853] tegra_pcie_port_reset: no rst_gpio------------------
[ 1.327895] tegra-pcie 10003000.pcie-controller: link 0 down, ignoring
[ 1.327897] PCIE: tegra_pcie_port_disable(2067)
[ 1.327901] PCIE: tegra_pcie_port_check_link(2172)
[ 1.733394] tegra-pcie 10003000.pcie-controller: link 1 down, retrying
[ 1.733398] PCIE: tegra_pcie_port_reset(2006)
[ 1.733400] tegra_pcie_port_reset: no rst_gpio------------------
[ 1.735434] tegra-pcie 10003000.pcie-controller: link 1 down, ignoring
[ 1.735436] PCIE: tegra_pcie_port_disable(2067)
[ 1.735440] PCIE: tegra_pcie_port_check_link(2172)
[ 2.141275] tegra-pcie 10003000.pcie-controller: link 2 down, retrying
[ 2.141278] PCIE: tegra_pcie_port_reset(2006)
[ 2.141280] tegra_pcie_port_reset: no rst_gpio------------------
[ 2.143317] tegra-pcie 10003000.pcie-controller: link 2 down, ignoring
[ 2.143319] PCIE: tegra_pcie_port_disable(2067)
[ 2.143326] PCIE: tegra_pcie_conf_gpios(2565)
[ 2.143331] tegra-pcie 10003000.pcie-controller: PCIE: no end points detected
[ 2.143336] PCIE: tegra_pcie_save_device(1838)
[ 2.143339] PCIE: tegra_pcie_prsnt_map_override(1101)
[ 2.143342] PCIE: tegra_pcie_prsnt_map_override(1101)
[ 2.143345] PCIE: tegra_pcie_prsnt_map_override(1101)
[ 2.143347] PCIE: tegra_pcie_pme_turnoff(1695)
[ 2.143413] PCIE: tegra_pcie_enable_pads(1441)
[ 2.143416] PCIE: tegra_pcie_unmap_resources(1653)
[ 2.143711] PCIE: tegra_pcie_module_power_off(1878)
[ 2.143713] PCIE: tegra_pcie_disable_regulators(1574)
[ 2.143718] tegra-pcie 10003000.pcie-controller: PCIE: Disable power rails
so I thought the pins would maintain high level if the following codes had been annotated:
static int tegra_pcie_save_device(struct device *dev)
{
struct tegra_pcie *pcie = dev_get_drvdata(dev);
struct tegra_pcie_port *port;
int err = 0;
PR_FUNC_LINE;
if (!pcie)
return 0;
if (pcie->pcie_power_enabled == 0) {
dev_info(dev, "PCIE: Already powered off");
pcie->pcie_power_enabled = 1; // xuxiaochuan
return 0;
}
list_for_each_entry(port, &pcie->ports, list) {
// tegra_pcie_prsnt_map_override(port, false);
}
// tegra_pcie_pme_turnoff(pcie);
// tegra_pcie_free_resources(pcie);
// tegra_pcie_enable_pads(pcie, false);
// tegra_pcie_unmap_resources(pcie);
// if (pcie->soc_data->config_pex_io_dpd) {
// err = pinctrl_select_state(pcie->pex_pin,
// pcie->pex_io_dpd_en_state);
// if (err < 0)
// dev_err(dev, "enabling pex-io-dpd failed: %d\n", err);
// }
// reset_control_assert(pcie->pciex_rst);
// reset_control_assert(pcie->pcie_rst);
// reset_control_assert(pcie->afi_rst);
// err = tegra_pcie_module_power_off(pcie);
// if (err < 0)
// dev_err(dev, "power off failed: %d\n", err);
// pm_clk_suspend(dev);
// tegra_pcie_config_plat(pcie, 0);
return err;
}
Then the log became as follow:
[ 0.808028] PCIE: tegra_pcie_probe(4848)
[ 0.808089] PCIE: tegra_pcie_read_plat_data(3330)
[ 0.808211] PCIE: tegra_pcie_parse_dt(3432)
[ 0.808336] tegra-pcie 10003000.pcie-controller: 1x1, 1x1, 1x1 configuration
[ 0.808405] PCIE: tegra_pcie_probe_complete(4728)
[ 0.808459] PCIE: tegra_pcie_init(2903)
[ 0.808486] PCIE: tegra_pcie_get_resources(1972)
[ 0.808515] PCIE: tegra_pcie_get_clocks(1302)
[ 0.809607] PCIE: tegra_pcie_enable_regulators(1552)
[ 0.809648] tegra-pcie 10003000.pcie-controller: PCIE: Enable power rails
[ 0.809773] PCIE: tegra_pcie_power_on(1825)
[ 0.809907] PCIE: tegra_pcie_restore_device(1766)
[ 0.809962] PCIE: tegra_pcie_module_power_on(1718)
[ 0.809991] PCIE: tegra_pcie_enable_regulators(1552)
[ 0.810019] PCIE: tegra_pcie_map_resources(1599)
[ 0.810072] PCIE: tegra_pcie_enable_pads(1441)
[ 0.810171] PCIE: tegra_pcie_enable_controller(1484)
[ 0.810273] PCIE: tegra_pcie_enable_msi(3143)
[ 0.810366] PCIE: tegra_pcie_check_ports(2543)
[ 0.810420] tegra-pcie 10003000.pcie-controller: probing port 0, using 1 lanes
[ 0.810462] PCIE: tegra_pcie_port_enable(2069)
[ 0.810492] PCIE: tegra_pcie_port_reset(1839)
[ 0.810520] tegra_pcie_port_reset: no rst_gpio------------------
[ 0.811802] PCIE: tegra_pcie_enable_rp_features(2412)
[ 0.811877] PCIE: tegra_pcie_enable_aer(1043)
[ 0.811914] PCIE: tegra_pcie_apply_sw_war(2254)
[ 0.814326] PCIE: tegra_pcie_prsnt_map_override(1101)
[ 0.814364] tegra-pcie 10003000.pcie-controller: probing port 1, using 1 lanes
[ 0.814426] PCIE: tegra_pcie_port_enable(2069)
[ 0.814456] PCIE: tegra_pcie_port_reset(1839)
[ 0.814484] tegra_pcie_port_reset: no rst_gpio------------------
[ 0.815799] PCIE: tegra_pcie_enable_rp_features(2412)
[ 0.815880] PCIE: tegra_pcie_enable_aer(1043)
[ 0.815918] PCIE: tegra_pcie_apply_sw_war(2254)
[ 0.816103] PCIE: tegra_pcie_prsnt_map_override(1101)
[ 0.816142] tegra-pcie 10003000.pcie-controller: probing port 2, using 1 lanes
[ 0.816182] PCIE: tegra_pcie_port_enable(2069)
[ 0.816210] PCIE: tegra_pcie_port_reset(1839)
[ 0.816237] tegra_pcie_port_reset: no rst_gpio------------------
[ 0.818315] PCIE: tegra_pcie_enable_rp_features(2412)
[ 0.818393] PCIE: tegra_pcie_enable_aer(1043)
[ 0.818426] PCIE: tegra_pcie_apply_sw_war(2254)
[ 0.820297] PCIE: tegra_pcie_prsnt_map_override(1101)
[ 0.839808] tegra-pcie 10003000.pcie-controller: link 0 down, ignoring
[ 0.839888] PCIE: tegra_pcie_port_disable(2100)
[ 0.839914] tegra-pcie 10003000.pcie-controller: link 1 down, ignoring
[ 0.839936] PCIE: tegra_pcie_port_disable(2100)
[ 0.839960] tegra-pcie 10003000.pcie-controller: link 2 down, ignoring
[ 0.839980] PCIE: tegra_pcie_port_disable(2100)
[ 0.840006] PCIE: tegra_pcie_conf_gpios(2595)
[ 0.840051] tegra-pcie 10003000.pcie-controller: PCIE: no end points detected
[ 0.840077] PCIE: tegra_pcie_save_device(1870)
But there was no change in waveform.I can’t figure out.
Any suggestion to maintain high level of the PEX_RST pins?
hello 295839633,
may I have more details about why you need to pull-up these two pins-PEX0_RST/PEX2_RST all the time
could you please add below gpio control in your kernel function to check if this workable?
gpio_set_value(port->rst_gpio, 1);
Sorry for replying late.
Thank you for your help.
I wanted to pull up the above pins, because they were used as enabling pins when connecting USB devices with these two PCIe interface according to the hardware design.
And I pulled up the pins on hardware finally.
Hello JerryChang
Thank you for answering the above questions.
Now I’m testing an eth controller card with PCIe interface, not pulling up the rst-pin.
There are 2 PCIe slots on my custom board, port_0 & port_2, and I modified the driver, pci-tegra.c, to set “1x1, 1x1, 1x1 configuration”
However no PCIe end points detected, ith the log as follow:
[ 0.471208] iommu: Adding device 10003000.pcie-controller to group 52
[ 0.471237] arm-smmu: forcing sodev map for 10003000.pcie-controller
[ 0.857857] PCIE: tegra_pcie_probe(4797)
[ 0.857891] PCIE: tegra_pcie_read_plat_data(3279)
[ 0.858038] PCIE: tegra_pcie_parse_dt(3381)
[ 0.858140] tegra-pcie 10003000.pcie-controller: 1x1, 1x1, 1x1 configuration
[ 0.858195] PCIE: tegra_pcie_probe_complete(4677)
[ 0.858217] PCIE: tegra_pcie_init(2854)
[ 0.858236] PCIE: tegra_pcie_get_resources(1938)
[ 0.858256] PCIE: tegra_pcie_get_clocks(1301)
[ 0.859292] PCIE: tegra_pcie_enable_regulators(1551)
[ 0.859324] tegra-pcie 10003000.pcie-controller: PCIE: Enable power rails
[ 0.859436] PCIE: tegra_pcie_power_on(1822)
[ 0.859569] PCIE: tegra_pcie_restore_device(1763)
[ 0.859594] PCIE: tegra_pcie_module_power_on(1715)
[ 0.859613] PCIE: tegra_pcie_enable_regulators(1551)
[ 0.859633] PCIE: tegra_pcie_map_resources(1596)
[ 0.859676] PCIE: tegra_pcie_enable_pads(1440)
[ 0.859768] PCIE: tegra_pcie_enable_controller(1483)
[ 0.859839] PCIE: tegra_pcie_enable_msi(3092)
[ 0.859922] PCIE: tegra_pcie_check_ports(2494)
[ 0.859993] tegra-pcie 10003000.pcie-controller: probing port 0, using 1 lanes
[ 0.860023] PCIE: tegra_pcie_port_enable(2022)
[ 0.860078] PCIE: tegra_pcie_port_reset(1993)
[ 0.862154] PCIE: tegra_pcie_enable_rp_features(2363)
[ 0.862199] PCIE: tegra_pcie_enable_aer(1042)
[ 0.862227] PCIE: tegra_pcie_apply_sw_war(2205)
[ 0.862564] PCIE: tegra_pcie_prsnt_map_override(1100)
[ 0.862593] tegra-pcie 10003000.pcie-controller: probing port 2, using 1 lanes
[ 0.862622] PCIE: tegra_pcie_port_enable(2022)
[ 0.862643] PCIE: tegra_pcie_port_reset(1993)
[ 0.864011] PCIE: tegra_pcie_enable_rp_features(2363)
[ 0.864052] PCIE: tegra_pcie_enable_aer(1042)
[ 0.864120] PCIE: tegra_pcie_apply_sw_war(2205)
[ 0.865136] PCIE: tegra_pcie_prsnt_map_override(1100)
[ 1.332664] tegra-pcie 10003000.pcie-controller: link 0 down, retrying
[ 1.332668] PCIE: tegra_pcie_port_reset(1993)
[ 1.739561] tegra-pcie 10003000.pcie-controller: link 0 down, retrying
[ 1.739564] PCIE: tegra_pcie_port_reset(1993)
[ 2.146472] tegra-pcie 10003000.pcie-controller: link 0 down, retrying
[ 2.146475] PCIE: tegra_pcie_port_reset(1993)
[ 2.148507] tegra-pcie 10003000.pcie-controller: link 0 down, ignoring
[ 2.148509] PCIE: tegra_pcie_port_disable(2053)
[ 2.553447] tegra-pcie 10003000.pcie-controller: link 2 down, retrying
[ 2.553450] PCIE: tegra_pcie_port_reset(1993)
[ 2.960463] tegra-pcie 10003000.pcie-controller: link 2 down, retrying
[ 2.960465] PCIE: tegra_pcie_port_reset(1993)
[ 3.454627] tegra-pcie 10003000.pcie-controller: link 2 down, retrying
[ 3.454631] PCIE: tegra_pcie_port_reset(1993)
[ 3.459136] tegra-pcie 10003000.pcie-controller: link 2 down, ignoring
[ 3.459138] PCIE: tegra_pcie_port_disable(2053)
[ 3.459145] PCIE: tegra_pcie_conf_gpios(2546)
[ 3.459150] tegra-pcie 10003000.pcie-controller: PCIE: no end points detected
[ 3.459152] PCIE: tegra_pcie_power_off(1901)
[ 3.459157] PCIE: tegra_pcie_save_device(1837)
[ 3.459159] PCIE: tegra_pcie_prsnt_map_override(1100)
[ 3.459162] PCIE: tegra_pcie_prsnt_map_override(1100)
[ 3.459165] PCIE: tegra_pcie_pme_turnoff(1694)
[ 3.459256] PCIE: tegra_pcie_enable_pads(1440)
[ 3.459260] PCIE: tegra_pcie_unmap_resources(1652)
[ 3.477899] PCIE: tegra_pcie_module_power_off(1877)
[ 3.477916] PCIE: tegra_pcie_disable_regulators(1573)
[ 3.477922] tegra-pcie 10003000.pcie-controller: PCIE: Disable power rails
I executed “lspci”, and got nothing too.
The power & rst signal of PEX were OK measured by the oscilloscope, but the ref_clk signal was not sent out when clk_req pin pulling down?
What may be the cause of the problem?
hello 295839633,
there’s erroneous in the documentation, please configure your PCIE settings as 1x2, 1x1, 1x1.
you might also refer to [url]Jetson/TX2 USB - eLinux.org for the USB lane mapping information correction.
thanks
Hi JerryChang
Thank you very much.
I’ve gotten both PCIe devices with the configuration you said.
But I also need to use USB_SS1 pin,it seems that only “1x1, 1x1, 1x1” configuration is available according to “USB Lane Mapping” and “pci-tegra.c”.
How to make PCIe pins work properly under “1x1, 1x1, 1x1” configuration?
On #2, you mentioned that:
Does it work?
And could p2771-0000.conf.common be flashed into tx2 just by:
./flash.sh -k kernel -K kernel/Image jetson-tx2 mmcblk0p1
hello 295839633,
you need to perform full-flash if you need to update the settings in p2771-0000.conf.common.
please check elinux page for an example of config#3 with 2x USB3.0 and 3x1 PCIe. thanks
Hi JerryChang
According to https://elinux.org/Jetson/TX2_USB#USB-Lane_Mapping, the plugin-manager log should be shown in my dmesg, but there was just:
nvidia@localhost:~$ dmesg | grep plugin-manager
[ 0.394173] Initializing plugin-manager
nvidia@localhost:~$
nvidia@localhost:~$
I modified tegra186-quill-p3310-1000-a00-plugin-manager.dtsi and flashed odmdata=0x6090000.
/ {
eeprom-manager {
data-size = <0x100>;
boardid-with-revision = <3310>;
boardid-with-config = <3310>;
bus@0 {
i2c-bus = <&gen8_i2c>;
eeprom@0 {
slave-address = <0x50>;
label = "cvm";
};
eeprom@1 {
slave-address = <0x57>;
label = "cvb";
};
};
bus@1 {
i2c-bus = <&gen2_i2c>;
eeprom@0 {
slave-address = <0x51>;
};
};
bus@2 {
i2c-bus = <&gen1_i2c>;
eeprom@0 {
slave-address = <0x50>;
};
};
bus@3 {
i2c-bus = <&cam_i2c>;
eeprom@0 {
slave-address = <0x54>;
label = "cam";
enable-gpio = <2 9>;
};
eeprom@1 {
slave-address = <0x57>;
label = "cam";
enable-gpio = <2 9>;
};
};
};
plugin-manager {
fragment-devslp@0 {
ids = ">=3310-1000-200";
override@0 {
target = <&{/ahci-sata@3507000}>;
_overlay_ {
gpios = <&spmic 7 0>;
};
};
override@1 {
target = <&{/bpmp_i2c/spmic@3c/pinmux@0}>;
_overlay_ {
pin_gpio7 {
drive-push-pull = <1>;
};
};
};
};
fragment-e3325-xusb {
enable-override-on-all-matches;
ids = "<3310-1000-500";
odm-data = "enable-xusb-on-uphy-lane0";
override@0 {
#if TEGRA_XUSB_PADCONTROL_VERSION >= DT_VERSION_2
target = <&xusb_padctl>;
_overlay_ {
ports {
usb2-2 {
status = "okay";
};
usb3-0 {
status = "okay";
};
};
};
#else
target = <&tegra_xusb_padctl_pinmux_default>;
_overlay_ {
e3325-usb3-std-A-HS {
status = "okay";
};
e3325-usb3-std-A-SS {
status = "okay";
};
};
#endif
};
override@1 {
target = <&{/xhci@3530000}>;
#if TEGRA_XUSB_PADCONTROL_VERSION >= DT_VERSION_2
_overlay_ {
phys = <&{/xusb_padctl@3520000/pads/usb2/lanes/usb2-0}>,
<&{/xusb_padctl@3520000/pads/usb2/lanes/usb2-1}>,
<&{/xusb_padctl@3520000/pads/usb2/lanes/usb2-2}>,
<&{/xusb_padctl@3520000/pads/usb3/lanes/usb3-0}>,
<&{/xusb_padctl@3520000/pads/usb3/lanes/usb3-1}>;
phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0", "usb3-1";
};
#else
_overlay_ {
phys = <&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(0)>,
<&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(1)>,
<&tegra_xusb_padctl TEGRA_PADCTL_PHY_USB3_P(1)>,
<&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(2)>,
<&tegra_xusb_padctl TEGRA_PADCTL_PHY_USB3_P(0)>;
phy-names = "utmi-0", "utmi-1", "usb3-1", "utmi-2", "usb3-0";
};
#endif
};
override@2 {
target = <&tegra_main_gpio>;
_overlay_ {
e3325_sdio_rst {
status = "okay";
};
e3325_lane0_mux {
status = "okay";
};
};
};
override@3 {
target = <&tegra_pcie>;
_overlay_ {
pci@1,0 {
nvidia,num-lanes = <1>;
};
pci@2,0 {
nvidia,num-lanes = <1>;
};
pci@3,0 {
nvidia,num-lanes = <1>;
};
};
};
};
fragment-500-pcie-config {
ids = ">=3310-1000-500";
override@0 {
target = <&tegra_pcie>;
_overlay_ {
pci@1,0 {
nvidia,num-lanes = <2>;
};
pci@2,0 {
nvidia,num-lanes = <1>;
};
pci@3,0 {
nvidia,num-lanes = <1>;
};
};
};
};
fragment-comms-a00-chip {
ids = "<3310-1000-500";
override@0 {
target = <&bcm4354>;
_overlay_ {
sdhci-host = <&sdmmc3>;
pwr-retry-cnt = <0>;
interrupt-parent = <&tegra_main_gpio>;
interrupts = <TEGRA_MAIN_GPIO(C, 0) 0x14>;
delete-target-property = "wlan-pwr-gpio";
};
};
override@1 {
target = <&tegra_main_gpio>;
_overlay_ {
wifi-wake-ap {
status = "okay";
gpios = <TEGRA_MAIN_GPIO(C, 0) 0>;
};
wifi-enable {
gpios = <TEGRA_MAIN_GPIO(B, 6) 0>;
};
};
};
override@3 {
target = <&tegra_aon_gpio>;
_overlay_ {
wifi-wake-ap {
status = "disabled";
};
};
};
};
fragment-500-xusb-config {
ids = ">=3310-1000-500";
override@0 {
target = <&{/xhci@3530000}>;
#if TEGRA_XUSB_PADCONTROL_VERSION >= DT_VERSION_2
_overlay_ {
phys = <&{/xusb_padctl@3520000/pads/usb2/lanes/usb2-0}>,
<&{/xusb_padctl@3520000/pads/usb2/lanes/usb2-1}>,
<&{/xusb_padctl@3520000/pads/usb3/lanes/usb3-0}>;
phy-names = "usb2-0", "usb2-1", "usb3-0";
};
#else
_overlay_ {
phys = <&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(0)>,
<&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(1)>,
<&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(2)>;
<&tegra_xusb_padctl TEGRA_PADCTL_PHY_USB3_P(1)>;
<&tegra_xusb_padctl TEGRA_PADCTL_PHY_USB3_P(2)>;
phy-names = "utmi-0", "utmi-1", "utmi-2", "usb3-1", "usb3-2";
};
#endif
};
override@1 {
#if TEGRA_XUSB_PADCONTROL_VERSION >= DT_VERSION_2
target = <&xusb_padctl>;
_overlay_ {
ports {
usb3-1 {
status = "disabled";
};
usb3-0 {
nvidia,usb2-companion = <1>;
status = "okay";
};
};
};
#else
target = <&tegra_xusb_padctl_pinmux_default>;
_overlay_ {
usb3-std-A-port2 {
nvidia,lanes = "usb3-1";
nvidia,port-cap = <TEGRA_PADCTL_PORT_HOST_ONLY>;
status = "okay";
};
usb3-std-A-port3 {
nvidia,lanes = "usb3-2";
nvidia,port-cap = <TEGRA_PADCTL_PORT_HOST_ONLY>;
status = "okay";
};
e3325-usb3-std-A-HS {
status = "okay";
};
};
#endif
};
};
fragment-500-e3325-pcie {
enable-override-on-all-matches;
ids = ">=3310-1000-500";
odm-data = "enable-pcie-on-uphy-lane0";
override@0 {
target = <&{/xhci@3530000}>;
#if TEGRA_XUSB_PADCONTROL_VERSION >= DT_VERSION_2
_overlay_ {
phys = <&{/xusb_padctl@3520000/pads/usb2/lanes/usb2-0}>,
<&{/xusb_padctl@3520000/pads/usb2/lanes/usb2-1}>;
phy-names = "usb2-0", "usb2-1";
};
#else
_overlay_ {
phys = <&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(0)>,
<&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(1)>,
<&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(2)>;
<&tegra_xusb_padctl TEGRA_PADCTL_PHY_USB3_P(1)>;
<&tegra_xusb_padctl TEGRA_PADCTL_PHY_USB3_P(2)>;
phy-names = "utmi-0", "utmi-1", "utmi-2", "usb3-1", "usb3-2";
};
#endif
};
override@1 {
target = <&tegra_xusb_padctl_pinmux_default>;
_overlay_ {
usb3-std-A-port2 {
nvidia,lanes = "usb3-1";
nvidia,port-cap = <TEGRA_PADCTL_PORT_HOST_ONLY>;
status = "okay";
};
usb3-std-A-port3 {
nvidia,lanes = "usb3-2";
nvidia,port-cap = <TEGRA_PADCTL_PORT_HOST_ONLY>;
status = "okay";
};
e3325-usb3-std-A-HS {
status = "okay";
};
};
};
override@2 {
target = <&tegra_main_gpio>;
_overlay_ {
pcie0_lane2_mux {
status = "okay";
};
};
};
};
fragment-e3320-dp {
ids = ">=3320-1000-000", ">=3320-1100-000";
override@0 {
target = <&{/host1x}>;
_overlay_ {
nvdisplay@15220000 {
status = "okay";
};
sor {
status = "okay";
dp-display {
status = "okay";
};
};
dpaux@155c0000 {
status = "okay";
};
};
};
};
fragment-p3310-c00-comm {
ids = ">=3310-1000-800";
override@0 {
target = <&{/bluedroid_pm}>;
_overlay_ {
bluedroid_pm,reset-gpio = <&tegra_main_gpio TEGRA_MAIN_GPIO(H, 5) 0>;
};
};
};
fragment-p3310-c00-pmic {
ids = ">=3310-1000-800";
override@0 {
target = <&spmic_ldo6>;
_overlay_ {
maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
};
};
};
fragment-p3310-c01 {
ids = ">=3310-1000-900";
override@0 {
target = <&{/bpmp_i2c/spmic@3c/regulators/ldo6}>;
_overlay_ {
regulator-boot-on;
regulator-always-on;
};
};
override@1 {
target = <&{/bpmp_i2c/spmic@3c/pinmux@0}>;
_overlay_ {
pin_gpio2 {
status = "disabled";
};
pin_gpio3 {
status = "disabled";
};
};
};
};
fragment-p3310-c03 {
ids = ">=3310-1000-B00";
override@1 {
target = <&spmic_ldo8>;
_overlay_ {
regulator-name = "dvdd-pex";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
};
};
override@2 {
target = <&spmic_ldo0>;
_overlay_ {
maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
};
};
override@3 {
target = <&spmic_ldo7>;
_overlay_ {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
};
};
};
};
};
[ 0.2908 ] Updating Odmdata
[ 0.2915 ] tegrabct_v2 --brbct br_bct_BR.bct --chip 0x18 0 --updatefields Odmdata =0x6090000
However, PEX0 & PEX2 solts worked while USB_SS1 didn’t work.
nvidia@localhost:~$ lspci
00:01.0 PCI bridge: NVIDIA Corporation Device 10e5 (rev a1)
00:02.0 PCI bridge: NVIDIA Corporation Device 10e6 (rev a1)
01:00.0 PCI bridge: ASMedia Technology Inc. Device 1182
02:03.0 PCI bridge: ASMedia Technology Inc. Device 1182
02:07.0 PCI bridge: ASMedia Technology Inc. Device 1182
03:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller (rev 07)
04:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller (rev 07)
05:00.0 Ethernet controller: Intel Corporation I350 Gigabit Network Connection (rev 01)
05:00.1 Ethernet controller: Intel Corporation I350 Gigabit Network Connection (rev 01)
nvidia@localhost:~$
nvidia@localhost:~$
----------------------------------------------------------------------------------------------------
nvidia@localhost:~$ lsusb -t
/: Bus 02.Port 1: Dev 1, Class=root_hub, Driver=tegra-xusb/3p, 5000M
/: Bus 01.Port 1: Dev 1, Class=root_hub, Driver=tegra-xusb/4p, 480M
nvidia@localhost:~$
nvidia@localhost:~$
And I read out lanes mapping:
odmdata=0x1090000
--------------------------------------------------------
nvidia@nvidia-desktop:~$ ./devmem.sh
[sudo] password for nvidia:
/dev/mem opened.
Memory mapped at address 0x7faf084000.
Value at address 0x2520284 (0x7faf084284): 0x0
/dev/mem opened.
Memory mapped at address 0x7fad155000.
Value at address 0x2530284 (0x7fad155284): 0x1
/dev/mem opened.
Memory mapped at address 0x7f9453d000.
Value at address 0x2540284 (0x7f9453d284): 0x1
/dev/mem opened.
Memory mapped at address 0x7fac975000.
Value at address 0x2550284 (0x7fac975284): 0x1
/dev/mem opened.
Memory mapped at address 0x7f8692f000.
Value at address 0x2560284 (0x7f8692f284): 0x1
/dev/mem opened.
Memory mapped at address 0x7f83f46000.
Value at address 0x2570284 (0x7f83f46284): 0x2
odmdata=0x6090000
---------------------------------------------------------
nvidia@nvidia-desktop:~$ ./devmem.sh
[sudo] password for nvidia:
/dev/mem opened.
Memory mapped at address 0x7f8ebf2000.
Value at address 0x2520284 (0x7f8ebf2284): 0x1
/dev/mem opened.
Memory mapped at address 0x7fa343e000.
Value at address 0x2530284 (0x7fa343e284): 0x0
/dev/mem opened.
Memory mapped at address 0x7f8477b000.
Value at address 0x2540284 (0x7f8477b284): 0x0
/dev/mem opened.
Memory mapped at address 0x7f7f1ec000.
Value at address 0x2550284 (0x7f7f1ec284): 0x1
/dev/mem opened.
Memory mapped at address 0x7fa2352000.
Value at address 0x2560284 (0x7fa2352284): 0x1
/dev/mem opened.
Memory mapped at address 0x7f822e6000.
Value at address 0x2570284 (0x7f822e6284): 0x2
And device tree value:
nvidia@nvidia-desktop:~$ xxd /proc/device-tree/pinctrl@3520000/pinmux/usb3-std-A-port3/nvidia\,lanes
00000000: 7573 6233 2d32 00 usb3-2.
nvidia@nvidia-desktop:~$
nvidia@nvidia-desktop:~$
nvidia@nvidia-desktop:~$ xxd /proc/device-tree/pinctrl@3520000/pinmux/usb3-std-A-port3/nvidia\,oc-pin
00000000: 0000 0001 ....
nvidia@nvidia-desktop:~$
nvidia@nvidia-desktop:~$
nvidia@nvidia-desktop:~$ xxd /proc/device-tree/pinctrl@3520000/pinmux/usb3-std-A-port3/nvidia\,port-cap
00000000: 0000 0001 ....
nvidia@nvidia-desktop:~$
nvidia@nvidia-desktop:~$
nvidia@nvidia-desktop:~$ xxd /proc/device-tree/pinctrl@3520000/pinmux/usb3-std-A-port3/status
00000000: 6f6b 6179 00 okay.
nvidia@nvidia-desktop:~$
nvidia@nvidia-desktop:~$
nvidia@nvidia-desktop:~$ xxd /proc/device-tree/pinctrl@3520000/pinmux/usb3-std-A-port3/name
00000000: 7573 6233 2d73 7464 2d41 2d70 6f72 7433 usb3-std-A-port3
00000010: 00 .
It seems that the odmdata has been updated correctly.
Well, is there any mistake in device tree causing that nothing could not be detected by USB_SS1(lane 2).
If you don’t have plugin-manager log in kernel log, it implies your are using rel-32.1 based release. Please confirm.
All the guidance here is currently for rel-28 based.
Hi JerryChang
I’m sorry for no mention of that the SDK is release 32.1.
So, what are the differences about “USB Lane Mapping” between R28.2 and R32.1?
The device tree has some different because rel-28 is k4.4 while rel-32 is k4.9. Would you mind moving to rel-28.2 to verify it first and then move back to rel-32?
Because we have less users verify usb lane mapping on rel-32 than rel-28, it would be better to check hardware capability on rel-28 first.
Hi Wayne,
Sorry for the delay.
I will give it a try as you say.
But now, I have another question. We are designing a solution that will use the Config.3 of USB Lane Mapping:2-USB3.0, 3×1-PCIe, 1-SATA.
Does the hardware & l4t-r32.1 of TX2 support the above configuration?
If not, will the subsequent updates support it?
Thank you!
Yes, such hw capability would not change when software release is changed.
Hi Wayne,
Thank you.
For some reason, I don’t have time to verify all the 6 configurations of USB Lane Mapping. I just find 3 configurations in “pci-tegra.c”:
else if (of_device_is_compatible(np, "nvidia,tegra186-pcie")) {
switch (lanes) {
case 0x010004:
dev_info(pcie->dev, "4x1, 1x1 configuration\n");
*xbar = AFI_PCIE_CONFIG_XBAR_CONFIG_X4_X0_X1;
return 0;
case 0x010102:
dev_info(pcie->dev, "2x1, 1x1, 1x1 configuration\n");
*xbar = AFI_PCIE_CONFIG_XBAR_CONFIG_X2_X1_X1;
return 0;
case 0x010101:
dev_info(pcie->dev, "1x1, 1x1, 1x1 configuration\n");
*xbar = AFI_PCIE_CONFIG_XBAR_CONFIG_X1_X1_X1;
return 0;
default:
dev_info(pcie->dev, "wrong configuration updated in DT,"
" switching to default 2x1, 1x1, 1x1 "
"configuration\n");
*xbar = AFI_PCIE_CONFIG_XBAR_CONFIG_X2_X1_X1;
update_rp_lanes(pcie, 0x010102);
return 0;
}
And as Jerry said on #8:
I’m unclear now about if “1x1, 1x1, 1x1 configuration” works.
So I want to confirm that Config.3 has been supported on TX2.