pinmux config for second USB3 (USB_SS2)

I cannot enable second USB3 (USB_SS2) port using pinmux generator from NVidia. Anybody had any luck with this?

Hi DmitriK,

Thanks for the post.
Pinmux sheet does not control pcie/usb lane mappings. This is being taken care of by xusb_padcntrl driver and xusb driver and pcie driver in general.

So, you don’t have to make any pinmux changes. We are checking on our side to validate USB3.0 on M2 Key E port.
I would like to know, how are trying to work on USB_SS2 on M2E? I mean which module you have plugged in? Is it provided by Nvidia or you are using some custom card?

Similar changes as below is needed to get it working. As I said earlier, we are still in the process of validating it. You can also try at your end

diff --git a/arch/arm64/boot/dts/tegra210-jetson-cv-base-p2597-2180-a00.dts b/arch/arm64/boot/dts/tegra210-jetson-cv-base-p2597-2180-a00.dts
index 159c14b…4ee36a8 100644
— a/arch/arm64/boot/dts/tegra210-jetson-cv-base-p2597-2180-a00.dts
+++ b/arch/arm64/boot/dts/tegra210-jetson-cv-base-p2597-2180-a00.dts
@@ -203,7 +203,7 @@

    pcie-controller {
            nvidia,wake-gpio = <&gpio TEGRA_GPIO(A, 2) 0>;
  •           nvidia,lane-map = <0x14>;
    
  •           nvidia,lane-map = <0x4>;
              dvdd-pex-pll-supply = <&max77620_ldo1>;
              l0-dvddio-pex-supply = <&max77620_ldo1>;
              l1-dvddio-pex-supply = <&max77620_ldo1>;
    

@@ -228,7 +228,7 @@
};

            pci@2,0 {
  •                   status = "okay";
    
  •                   status = "disabled";
              };
      };
    

@@ -478,9 +478,9 @@
};

    xusb_pad_ctl: xusb_padctl { /* Put common control config here */
  •           nvidia,ss_portmap = <0x21>;
    
  •           nvidia,lane_owner = <0xff56>; /* Use 0xF to disable lane assign */
    
  •           nvidia,lane-map = <0x14>;
    
  •           nvidia,ss_portmap = <0x321>;
    
  •           nvidia,lane_owner = <0xf056>; /* Use 0xF to disable lane assign */
    
  •           nvidia,lane-map = <0x4>;
              nvidia,enable-sata-port;
              status = "okay";
      };
    

@@ -490,7 +490,7 @@
/* nvidia,gpio_controls_muxed_ss_lanes; /
nvidia,gpio_ss1_sata = <0>;
nvidia,ulpicap = <0>; /
No ulpi support. can we remove */

  •           nvidia,portmap = <0x0e03>;
    
  •           nvidia,portmap = <0x0e07>;
              nvidia,common_padctl = <&xusb_pad_ctl>;
              status = "okay";
      };
    

regards
Bibek

Hi Basu,

Following up on Dmitri’s post (He and I are working on the same project).

We’re set up very similarly to the TX1 Devkit:

We’ve co-opted the same set of signals for the first super speed USB port as the TX1 Kit:

Your Schematics (and the SOM symbol) have these labeled USB_SS0. These both go to the USB Type A connector on our design and the TX1 Dev kit.

Now, where I suspect the problem is:

We have a second USB 3.0 Type A using USB_SS1. These are the D42 / D43, G42, G43 Pairs. As I’m sure Dmitri has communicated, this port functions fine at High Speeds but does not work when both USB2_D and USB1_D are utilized (using what’s labeled USB2_D in the dev kit, pins B42/B43). My guess is that those lines are still being Co-opted for PCIE (As they’re additionally labeled PEX_TX3 and originally went to the PCIE connector on the TX1 Dev kit.

Now, I might confused but I think that puts us using USB_SS0 and USB_SS1 exclusively. Unless you’re enumerating those differently in software (which is possible) we aren’t using USB_SS2 at all (nor do I see it on your devkit schematic)

TLDR;

We’re Using USB SS0 on Pins F43/F44, C43/C44 and USB SS1 on Pins G42/G43 and D42/D43

Does that clarify it a bit?

Correction, I see that Dmitri is calling this USB_SS2. I’m not aware if that’s how those pins are referenced in kernel, but the above pinout / signaling descriptions should be treated as a ground truth.

USB Signal/pin names from TX1 Module Datasheet:

http://screencast.com/t/v6fsEuefm

Bibek,
The patch enabled USB_SS2, but in USB2 mode only, not SS.
Is there a fix for SS?

The module which we are using on M2E has both pcie and usb port coming out. And along with lane mapping there is a gpio which dictates the selection of pcie or usb port on M2E.
Can you try with this change.

diff --git a/arch/arm64/boot/dts/tegra210-jetson-cv-base-p2597-2180-a00.dts b/arch/arm64/boot/dts/tegra210-jetson-cv-base-p2597-2180-a00.dts
index dcd2535…ff49fff 100644
— a/arch/arm64/boot/dts/tegra210-jetson-cv-base-p2597-2180-a00.dts
+++ b/arch/arm64/boot/dts/tegra210-jetson-cv-base-p2597-2180-a00.dts
@@ -211,7 +211,7 @@
pcie-controller {
nvidia,wake-gpio = <&gpio TEGRA_GPIO(A, 2) 0>;

  •           nvidia,lane-map = <0x14>;
    
  •           nvidia,lane-map = <0x4>;
              dvdd-pex-pll-supply = <&max77620_ldo1>;
              l0-dvddio-pex-supply = <&max77620_ldo1>;
              l1-dvddio-pex-supply = <&max77620_ldo1>;
    

@@ -486,9 +486,9 @@
};
xusb_pad_ctl: xusb_padctl { /* Put common control config here */

  •           nvidia,ss_portmap = <0x21>;
    
  •           nvidia,lane_owner = <0xff56>; /* Use 0xF to disable lane assign */
    
  •           nvidia,lane-map = <0x14>;
    
  •           nvidia,ss_portmap = <0x321>;
    
  •           nvidia,lane_owner = <0xf056>; /* Use 0xF to disable lane assign */
    
  •           nvidia,lane-map = <0x4>;
              nvidia,enable-sata-port;
              status = "okay";
      };
    

@@ -498,7 +498,7 @@
/* nvidia,gpio_controls_muxed_ss_lanes; /
nvidia,gpio_ss1_sata = <0>;
nvidia,ulpicap = <0>; /
No ulpi support. can we remove */

  •           nvidia,portmap = <0x0e03>;
    
  •           nvidia,portmap = <0x0e07>;
              nvidia,common_padctl = <&xusb_pad_ctl>;
              status = "okay";
      };
    

diff --git a/drivers/usb/host/xhci-tegra.c b/drivers/usb/host/xhci-tegra.c
index 8b81f00…66a054c 100644
— a/drivers/usb/host/xhci-tegra.c
+++ b/drivers/usb/host/xhci-tegra.c
@@ -5318,6 +5318,14 @@ static int tegra_xhci_probe(struct platform_device *pdev)
#endif
int partition_id_xusba, partition_id_xusbc;

  •   {
    
  •           int ret;
    
  •           ret = gpio_request(66, "gps_en");
    
  •           gpio_direction_output(66, 0);
    
  •    }
    
  •   if (tegra_platform_is_fpga())
              xusb_tegra_program_registers();
    

regards
Bibek

Bibek, patch failed to apply for xhci-tegra.c. You are using different code base.
I am using r23.2 release.

git log drivers/usb/host/xhci-tegra.c
commit a56757db7192458041556ca1d3fea4880b572783
Author: TW Chiu twchiu@nvidia.com
Date: Mon Nov 30 13:59:57 2015 +0800

Hi Dmitri,

Just add the below code in tegra_xhci_probe function at the starting

  • {
  • int ret;
  • ret = gpio_request(66, “gps_en”);
  • gpio_direction_output(66, 0);
  • }

Anyway, I have attached the patch. Please try plugging the 3.0 usb after system boots.
From 2a9b87a04a2c928cbf331e7d1156e24276a50a4a Mon Sep 17 00:00:00 2001
From: Bibek Basu bbasu@nvidia.com
Date: Mon, 2 May 2016 17:26:38 +0530
Subject: [PATCH] driver: usb: tegra-xhci debug patch

enable USB_SS2 on M2 Key E port

Change-Id: I77e792731a62c2131a77e1b71159d0c24421cb8d
Signed-off-by: Bibek Basu bbasu@nvidia.com

arch/arm64/boot/dts/tegra210-jetson-cv-base-p2597-2180-a00.dts | 10 ++++±----
drivers/usb/host/xhci-tegra.c | 5 +++++
2 files changed, 10 insertions(+), 5 deletions(-)

diff --git a/arch/arm64/boot/dts/tegra210-jetson-cv-base-p2597-2180-a00.dts b/arch/arm64/boot/dts/tegra210-jetson-cv-base-p2597-2180-a00.dts
index 2a8f8f38…67406ba 100644
— a/arch/arm64/boot/dts/tegra210-jetson-cv-base-p2597-2180-a00.dts
+++ b/arch/arm64/boot/dts/tegra210-jetson-cv-base-p2597-2180-a00.dts
@@ -194,7 +194,7 @@

pcie-controller {
	nvidia,wake-gpio = <&gpio TEGRA_GPIO(A, 2) 0>;
  •   nvidia,lane-map = <0x14>;
    
  •   nvidia,lane-map = <0x4>;
      dvdd-pex-pll-supply = <&max77620_ldo1>;
      l0-dvddio-pex-supply = <&max77620_ldo1>;
      l1-dvddio-pex-supply = <&max77620_ldo1>;
    

@@ -424,9 +424,9 @@
};

xusb_pad_ctl: xusb_padctl { /* Put common control config here */
  •   nvidia,ss_portmap = <0x21>;
    
  •   nvidia,lane_owner = <0xff56>; /* Use 0xF to disable lane assign */
    
  •   nvidia,lane-map = <0x14>;
    
  •   nvidia,ss_portmap = <0x321>;
    
  •   nvidia,lane_owner = <0xf056>; /* Use 0xF to disable lane assign */
    
  •   nvidia,lane-map = <0x4>;
      nvidia,enable-sata-port;
      status = "okay";
    
    };
    @@ -436,7 +436,7 @@
    /* nvidia,gpio_controls_muxed_ss_lanes; /
    nvidia,gpio_ss1_sata = <0>;
    nvidia,ulpicap = <0>; /
    No ulpi support. can we remove */
  •   nvidia,portmap = <0x0e03>;
    
  •   nvidia,portmap = <0x0e07>;
      nvidia,common_padctl = <&xusb_pad_ctl>;
      status = "okay";
    

    };
    diff --git a/drivers/usb/host/xhci-tegra.c b/drivers/usb/host/xhci-tegra.c
    index 52c5144…56ddb07 100644
    — a/drivers/usb/host/xhci-tegra.c
    +++ b/drivers/usb/host/xhci-tegra.c
    @@ -5163,7 +5163,12 @@ static int tegra_xhci_probe(struct platform_device *pdev)
    #if defined(CONFIG_ARCH_TEGRA_21x_SOC)
    u32 port;
    #endif

  • {

  •   int ret;
    
  • ret = gpio_request(66, “gps_en”);

  • gpio_direction_output(66, 0);

  • }
    if (tegra_platform_is_fpga())
    xusb_tegra_program_registers();


2.1.4

regards
Bibek

Did not help, still USB2.

Also, your 2nd & 3rd patches are missing these lines from the 1st patch:

	pci@2,0 {
  •   	status = "okay";
    
  •   	status = "disabled";
      };
    

intentional?

Yes,Intentional.

Can you attach a pic of your setup?

Basu,

Could you be a bit more specific? We’d be happy to snap a picture of the setup (this is a custom carrier FYI), but I’m not sure that’ll cover the information you are looking for.

I want to see where and how are you using USB_SS2.
Please send a pic of the setup of Jetson TX1 with USB in question connected.
You can also mail to bbasu@nvidia.com if its something you dont want to share publicly.

regards
Bibek

this issue is solved now with below change to use lane 3 which is a mux between PCIE0_Lane 1 and USB_SS2. So Make below change in DT file and try.

diff --git a/arch/arm64/boot/dts/tegra210-jetson-cv-base-p2597-2180-a00.dts b/arch/arm64/boot/dts/tegra210-jetson-cv-base-p2597-2180-a00.dts
index 159c14b…24eaeb9 100644
— a/arch/arm64/boot/dts/tegra210-jetson-cv-base-p2597-2180-a00.dts
+++ b/arch/arm64/boot/dts/tegra210-jetson-cv-base-p2597-2180-a00.dts
@@ -203,7 +203,7 @@

            pcie-controller {
                           nvidia,wake-gpio = <&gpio TEGRA_GPIO(A, 2) 0>;
  •                          nvidia,lane-map = <0x14>;
    
  •                         nvidia,lane-map = <0x12>;
                             dvdd-pex-pll-supply = <&max77620_ldo1>;
                             l0-dvddio-pex-supply = <&max77620_ldo1>;
                             l1-dvddio-pex-supply = <&max77620_ldo1>;
    

@@ -478,9 +478,9 @@
};

            xusb_pad_ctl: xusb_padctl { /* Put common control config here */
  •                          nvidia,ss_portmap = <0x21>;
    
  •                          nvidia,lane_owner = <0xff56>; /* Use 0xF to disable lane assign */
    
  •                          nvidia,lane-map = <0x14>;
    
  •                         nvidia,ss_portmap = <0x221>;
    
  •                         nvidia,lane_owner = <0xf356>; /* Use 0xF to disable lane assign */
    
  •                         nvidia,lane-map = <0x12>;
                             nvidia,enable-sata-port;
                             status = "okay";
             };
    

@@ -490,7 +490,7 @@
/* nvidia,gpio_controls_muxed_ss_lanes; /
nvidia,gpio_ss1_sata = <0>;
nvidia,ulpicap = <0>; /
No ulpi support. can we remove */

  •                          nvidia,portmap = <0x0e03>;
    
  •                         nvidia,portmap = <0x0e07>;
                             nvidia,common_padctl = <&xusb_pad_ctl>;
                             status = "okay";
             };

Hi,

We are trying to make a similar change in pin configuration. In our case we want to mux PCIE0 and USB_SS2. This corresponds to configuration 3 on Table 12 of OEM product design guide. So, the pins H42,H41,E42,E41 (rx-,rx+,tx-,tx+) will be used for the second USB3.0 port. How can we make this change; can you provide a patch for this too?

Regards,
Talha

Hello, Talha:
Please take a look at https://devtalk.nvidia.com/default/topic/925646/jetson-tx1/tx1-usb3-0-design/post/4864090/#4864090
It may help.

br
ChenJian

Thanks ChenJian.

I came across that post after posting here. From that information, I figured out the changes I need (except for the lane-map variable); I list them below.

nvidia,ss_portmap
0x321 0000 0011 0010 0001
nvidia, lane_owner
0xF056 0000 0000 1111 0000 0101 0110
nvidia, portmap
0x0e07 0000 0000 0000 1110 0000 0111

I could not figure out how lane-map should be configured both in the pcie controller and xusb_pad_ctl part in tegra210-jetson-cv-base-p2597-2180-a00.dts . Could you give some information on nvidia,lane-map variable?

Using the one which is suggested by Bibek earlier in this post (0x4), I was able to get the correct configuration on the USB ports, meaning that they were recognizing USB3.0 devices as desired. However the performance is really low, even lower than what a USB2.0 interface would give. And this is true for both ports. Initially, by default configuration, port 1 was working properly as USB3.0.

Currently, I am trying different things with the device tree and testing on the board (e.g. disabling pcie, sata, usb2.0 interfaces), but no results so far. I also tried the patch Bibek suggested on xhci-tegra.c with no luck.

I carried out the tests on L4T R23.2 kernel, and I will also try them on R24.1 .

Would you have any other suggestions?

Thanks,
Talha

Hello, Talha:
Would you please take a look at released document: http://developer.nvidia.com/embedded/dlc/l4t-documentation-24-2
there’s a PDF named ‘Platform Adaptation and Bring-Up Guide’. It provides detailed explanation about DTS props you mentioned. Also, some examples are included.

Please let me know if there’s any further problem.

br
Chenjian

Hello nVIDIA,

Sorry to bring up the thread again.

I’m referring to PLATFORM ADAPTATION AND BRING-UP GUIDE (DA_07839-001_01 | September 12, 2016), Page 15/16.

I’m not yet able get the bitwise description for nvidia,lane-map. I see there are descriptions for nvidia,ss_portmap, nvidia,lane_owner and nvidia,portmap.

Please provide the full description of nvidia,lane-map same as the other three I mentioned, it’d be very helpful.

Thanks,
Hakim

I think it works by this way

nvidia,lane-map = 0xPQ

where Q and P nibble is number of PCIe lanes of PCIe-0 and PCIe-1 respectively.

So,

nvidia,lane-map = 0x14 means PCIe-0 has x4 lane and PCIe-1 has x1 lane

Let me know if this is not correct.

Hakim

Hello,

By using the above config and rebuild the dtb file,
I get the following result:

ubuntu@tegra-ubuntu:~$ dmesg | grep pcie
[ 0.202918] platform 1003000.pcie-controller: domain=ffffffc0fe264d58 allocates as[0]=ffffffc0fe1803e8
[ 0.588030] tegra-pcie 1003000.pcie-controller: PCIE: Enable power rails
[ 0.588868] tegra-pcie 1003000.pcie-controller: probing port 0, using 4 lanes and lane map as 0x12
[ 0.590931] tegra-pcie 1003000.pcie-controller: probing port 1, using 1 lanes and lane map as 0x12
[ 0.613035] tegra-pcie 1003000.pcie-controller: link 0 down, ignoring
[ 0.613046] tegra-pcie 1003000.pcie-controller: link 1 down, ignoring
[ 0.613055] tegra-pcie 1003000.pcie-controller: PCIE: no ports detected
[ 0.613248] tegra-pcie 1003000.pcie-controller: PCIE: Disable power rails

Is the “port 0, using 4 lanes” correct?
Does it should be “port 0, using 1 lane”?
Thanks a lot.