TX2 USB/PCIe Lane Mapping configs #3(JetPack 3.3)

superlee1212 · February 14, 2019, 3:35am

Hi Sir/Madam,

I would like to config USB Lane Mapping to #3 so I follow other threads to modify ODMDATA to 0x06090000 in “p2771-0000.conf.common” and modify the following parts in “tegra186-quill-p3310-1000-a00-00-base.dts” and “tegra186-quill-p3310-1000-c03-00-base.dts”.

I refer to https://devtalk.nvidia.com/default/topic/1029115/jetson-tx2/tx2-usb-lane-mapping-configs-4/post/5235474/#5235474

in “tegra186-quill-p3310-1000-c03-00-base.dts”

gpio@2200000 {
		sdmmc-wake-support-input {
			status = "okay";
		};

		sdmmc-wake-support-output {
			status = "okay";
		};
		
		pcie0_lane2_mux {
			gpio-hog;
			gpios = <TEGRA_MAIN_GPIO(R, 3) 0>;
			output-low;
			label = "pcie-lane2-mux";
			status = "okay"; //this is for switch from usb3.0 to x1 PCIe on M.2.
		};

pcie-controller@10003000 {
		pci@1,0 {
			nvidia,num-lanes = <1>;
			nvidia,disable-clock-request;
			status = "okay";
		};
		pci@2,0 {
			nvidia,num-lanes = <1>;
			status = "okay";
		};
		pci@3,0 {
			nvidia,num-lanes = <1>;
			status = "okay";
		};
	};

        xhci@3530000 {
		phys = <&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(0)>,
			<&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(1)>,
			<&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(2)>,
			<&tegra_xusb_padctl TEGRA_PADCTL_PHY_USB3_P(1)>,
			<&tegra_xusb_padctl TEGRA_PADCTL_PHY_USB3_P(2)>;
		phy-names = "utmi-0", "utmi-1", "utmi-2", "usb3-1", "usb3-2";
	};

	pinctrl@3520000 {
		pinmux {
			usb3-std-A-port2 {
				nvidia,lanes = "usb3-1";
				nvidia,port-cap = <TEGRA_PADCTL_PORT_HOST_ONLY>;
				status = "okay";
			};

			usb3-std-A-port3 {
				nvidia,lanes = "usb3-2";
				nvidia,port-cap = <TEGRA_PADCTL_PORT_HOST_ONLY>;
				status = "okay";
			};

			e3325-usb3-std-A-HS {
				status = "okay"; //this is usb2.0 port on M.2.
			};		
		};
	};

in “tegra186-quill-p3310-1000-a00-00-base.dts”

xhci@3530000 {
		status = "okay";
		phys = <&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(0)>,
			<&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(1)>,
			<&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(2)>,
			<&tegra_xusb_padctl TEGRA_PADCTL_PHY_USB3_P(1)>,
			<&tegra_xusb_padctl TEGRA_PADCTL_PHY_USB3_P(2)>;
		phy-names = "utmi-0", "utmi-1", "utmi-2", "usb3-1", "usb3-2";
		nvidia,boost_cpu_freq = <800>;
	};

pinctrl@3520000 {
		status = "okay";
		pinctrl-0 = <&tegra_xusb_padctl_pinmux_default>;
		pinctrl-1 = <&vbus_en0_sfio_tristate_state>;
		pinctrl-2 = <&vbus_en1_sfio_tristate_state>;
		pinctrl-3 = <&vbus_en0_sfio_passthrough_state>;
		pinctrl-4 = <&vbus_en1_sfio_passthrough_state>;
		pinctrl-5 = <&vbus_en0_default_state>;
		pinctrl-6 = <&vbus_en1_default_state>;
		pinctrl-names = "default",
			"vbus_en0_sfio_tristate", "vbus_en1_sfio_tristate",
			"vbus_en0_sfio_passthrough", "vbus_en1_sfio_passthrough",
			"vbus_en0_default", "vbus_en1_default";
		tegra_xusb_padctl_pinmux_default: pinmux {
			/* Quill does not support usb3-micro AB */
			usb2-micro-AB {
				nvidia,lanes = "otg-0";
				nvidia,function = "xusb";
				nvidia,port-cap = <TEGRA_PADCTL_PORT_OTG_CAP>;
				nvidia,oc-pin = <0>;
			};
			usb2-std-A-port2 {
				nvidia,lanes = "otg-1";
				nvidia,function = "xusb";
				nvidia,port-cap = <TEGRA_PADCTL_PORT_HOST_ONLY>;
				nvidia,oc-pin = <1>;
			};
			usb3-std-A-port2 {
				nvidia,lanes = "usb3-1";
				nvidia,port-cap = <TEGRA_PADCTL_PORT_HOST_ONLY>;
				nvidia,oc-pin = <1>;
			};

			usb3-std-A-port3 {
				nvidia,lanes = "usb3-2";
				nvidia,port-cap = <TEGRA_PADCTL_PORT_HOST_ONLY>;
				status = "okay";
			};

			e3325-usb3-std-A-HS {
				nvidia,lanes = "otg-2";
				nvidia,function = "xusb";
				nvidia,port-cap = <TEGRA_PADCTL_PORT_HOST_ONLY>;
				status = "okay";
			};

		};
	};
	pcie-controller@10003000 {
		status = "okay";
		pci@1,0 {
			nvidia,num-lanes = <1>;
			status = "okay";
		};
		pci@2,0 {
			nvidia,num-lanes = <1>;
			status = "okay";
		};
		pci@3,0 {
			nvidia,num-lanes = <1>;
			status = "okay";
		};
	};

2、 I connected an i210 NIC to each pceix1 in pcie#0_0, pcie#1_0 pcie#2_0， rebuild dtbs and flash
I used the dmesg command to get the following information.

nvidia@tegra-ubuntu:~$ dmesg | grep pci
[    0.265901] GPIO line 459 (pcie-lane2-mux) hogged as output/low
[    0.269470] iommu: Adding device 10003000.pcie-controller to group 50
[    7.640183] tegra-pcie 10003000.pcie-controller: 1x1, 1x1, 1x1 configuration
[    7.652543] tegra-pcie 10003000.pcie-controller: PCIE: Enable power rails
[    7.688605] tegra-pcie 10003000.pcie-controller: probing port 0, using 1 lanes
[    7.690558] tegra-pcie 10003000.pcie-controller: probing port 1, using 1 lanes
[    7.692771] tegra-pcie 10003000.pcie-controller: probing port 2, using 1 lanes
[    8.156366] tegra-pcie 10003000.pcie-controller: link 0 down, retrying
[    8.560392] tegra-pcie 10003000.pcie-controller: link 0 down, retrying
[    8.986369] tegra-pcie 10003000.pcie-controller: link 0 down, retrying
[    8.988397] tegra-pcie 10003000.pcie-controller: link 0 down, ignoring
[    9.387991] tegra-pcie 10003000.pcie-controller: link 2 down, retrying
[    9.792389] tegra-pcie 10003000.pcie-controller: link 2 down, retrying
[   10.204424] tegra-pcie 10003000.pcie-controller: link 2 down, retrying
[   10.206440] tegra-pcie 10003000.pcie-controller: link 2 down, ignoring
[   10.206795] tegra-pcie 10003000.pcie-controller: PCI host bridge to bus 0000:00

But I can only find one i210 NIC using the lspci command.

nvidia@tegra-ubuntu:~$ lspci
00:02.0 PCI bridge: NVIDIA Corporation Device 10e6 (rev a1)
01:00.0 Ethernet controller: Intel Corporation I210 Gigabit Network Connection (rev 03)

4、 I used the devmem2 command to get the lane mapping information.

root@tegra-ubuntu:~# ./devmem2 0x02520284 b
/dev/mem opened.
Memory mapped at address 0x7f7fe8d000.
Value at address 0x2520284 (0x7f7fe8d284): 0x0
root@tegra-ubuntu:~# ./devmem2 0x02530284 b 
/dev/mem opened.
Memory mapped at address 0x7fb6cb5000.
Value at address 0x2530284 (0x7fb6cb5284): 0x1
root@tegra-ubuntu:~# ./devmem2 0x02540284 b 
/dev/mem opened.
Memory mapped at address 0x7f9e10d000.
Value at address 0x2540284 (0x7f9e10d284): 0x1
root@tegra-ubuntu:~# ./devmem2 0x02550284 b 
/dev/mem opened.
Memory mapped at address 0x7f904a7000.
Value at address 0x2550284 (0x7f904a7284): 0x1
root@tegra-ubuntu:~# ./devmem2 0x02560284 b 
/dev/mem opened.
Memory mapped at address 0x7f85937000.
Value at address 0x2560284 (0x7f85937284): 0x1
root@tegra-ubuntu:~# ./devmem2 0x02570284 b 
/dev/mem opened.
Memory mapped at address 0x7f95d2b000.
Value at address 0x2570284 (0x7f95d2b284): 0x2

It still seems to be PCIe x 4 mode

I need help!

superlee1212 · February 14, 2019, 4:16am

Then I follow description in https://devtalk.nvidia.com/default/topic/1046417/jetson-tx2/usb-lane-mapping-for-config-4-on-tx2-r28-2/post/5310342/#5310342

it seems to work!

nvidia@tegra-ubuntu:~$ lspci
00:01.0 PCI bridge: NVIDIA Corporation Device 10e5 (rev a1)
00:02.0 PCI bridge: NVIDIA Corporation Device 10e6 (rev a1)
01:00.0 Ethernet controller: Intel Corporation I210 Gigabit Network Connection (rev 03)
02:00.0 Ethernet controller: Intel Corporation I210 Gigabit Network Connection (rev 03)

find two network cards

However, lane0 (pex1) still does not work. Using an oscilloscope to detect pci2 seems to be reset twice, and two reset signals appear.

If I want to switch to pex1, QSPI_IO2 gpio pin is set to high or low？ I did not find a description of the problem on any datasheet

WayneWWW · February 14, 2019, 6:11am

pcie0_lane2_mux should be set to “okay”. Could you share the full dmesg to me?

https://elinux.org/Jetson/TX2_USB

Have you disabled the plugin-manager? Please read the section of above link.

superlee1212 · February 14, 2019, 6:37am

yes! I have disabled the plugin-manager!

Also, I attach files–> dmesg.log boot.log

boot.log (91 KB)
dmesg.log (71.5 KB)
tegra186-quill-p3310-1000-a00-plugin-manager.dtsi.txt (6.79 KB)

WayneWWW · February 14, 2019, 7:28am

Don’t see much error in dmesg. Plugin-manager is confirmed disabled.

How about the odm data?
Could you share the result of

nvidia@tegra-ubuntu:/proc/device-tree/chosen/plugin-manager/odm-data$ ls

You could also check other run-time device tree value under /proc/device-tree/

superlee1212 · February 14, 2019, 9:20am

Hi WanyeWWW

nvidia@tegra-ubuntu:/proc/device-tree/chosen/plugin-manager/odm-data$ 
nvidia@tegra-ubuntu:/proc/device-tree/chosen/plugin-manager/odm-data$ ls -l
total 0
-r--r--r-- 1 root root 4 Feb 13 02:03 android-build
-r--r--r-- 1 root root 4 Feb 13 02:03 disable-pmic-wdt
-r--r--r-- 1 root root 4 Feb 13 02:03 disable-sdmmc-hwcq
-r--r--r-- 1 root root 4 Feb 13 02:03 disable-tegra-wdt
-r--r--r-- 1 root root 4 Feb 13 02:03 enable-debug-console
-r--r--r-- 1 root root 4 Feb 13 02:03 enable-denver-wdt
-r--r--r-- 1 root root 4 Feb 13 02:03 enable-pcie-on-uphy-lane1
-r--r--r-- 1 root root 4 Feb 13 02:03 enable-pcie-on-uphy-lane2
-r--r--r-- 1 root root 4 Feb 13 02:03 enable-pcie-on-uphy-lane4
-r--r--r-- 1 root root 4 Feb 13 02:03 enable-sata-on-uphy-lane5
-r--r--r-- 1 root root 4 Feb 13 02:03 enable-xusb-on-uphy-lane0
-r--r--r-- 1 root root 9 Feb 13 02:03 name
-r--r--r-- 1 root root 4 Feb 13 02:03 no-battery
-r--r--r-- 1 root root 4 Feb 13 02:03 normal-flashed
nvidia@tegra-ubuntu:/proc/device-tree/chosen/plugin-manager/odm-data$

Is the odmdata information incorrect?

enable-pcie-on-uphy-lane1
enable-pcie-on-uphy-lane2
enable-pcie-on-uphy-lane4
enable-sata-on-uphy-lane5
enable-xusb-on-uphy-lane0-------here???

in file “p2771-0000.conf.common”

process_board_version()
{
	local board_id="${1}";
	local board_version="${2}";
	local bdv=${board_version^^};
	local bid=${board_id^^};
	local uboot_build=500;
	local fromfab="-a00";
	local tofab="-c03";		# default = C03
	local pmicfab="-c00";		# default = C00
	local bpfdtbfab="-c00";		# default = C00
	local tbcdtbfab="-c03";		# default = C03
	local kerndtbfab="-c03";	# default = C03
	ODMDATA=0x6090000;		# default = C0X
					# change by crengby lee 2019-1-17, for configs #3

I have already changed OSMDATA to 0x6090000…
Reflash does not take effect?

superlee1212 · February 14, 2019, 9:35am

Hi WanyeWWW

In file “JetsonTX2_TX2i_OEM_Product_Design_Guide_20180618.pdf” Figure 17. PCIe Connection Example Page 30,

It is described that the PMIC GPIO7 controls the MUX to switch between the signal SATA_DEV_SLP and the signal PEX1_CLKREQ#.
There is no data showing whether there is any relationship with this signal.

WayneWWW · February 14, 2019, 9:39am

The odm data is wrong. Could you share what command you are using to flash?

superlee1212 · March 8, 2019, 9:31am

Hi WayneWWW,

thank you, it works

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TX2 USB/PCIe Lane Mapping configs #3(JetPack 3.3)

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