- How can I assign PCIe#2 to PEX0 Lane 0 and usb3-1 to PEX_RFU Lane 1?
XUSB is being assigned to lane0 instead of lane 1 even though I set ODMDATA=0x2090000 in p2771-0000.conf.common!
The following is what I see with the TX2i on our board with the changes to .dts configuration files shown below.
nvidia@tegra-ubuntu:~$ ls /proc/device-tree/chosen/plugin-manager/odm-data/
android-build disable-sdmmc-hwcq enable-debug-console enable-pcie-on-uphy-lane1 enable-pcie-on-uphy-lane4 enable-xusb-on-uphy-lane0 no-battery
disable-pmic-wdt disable-tegra-wdt enable-denver-wdt enable-pcie-on-uphy-lane2 enable-sata-on-uphy-lane5 name normal-flashed
nvidia@tegra-ubuntu:~$ xxd /proc/device-tree/pinctrl@3520000/pinmux/usb3-std-A-port2/nvidia,lanes
00000000: 7573 6233 2d31 00 usb3-1.
nvidia@tegra-ubuntu:~$ sudo devmem2 0x02520284 b
/dev/mem opened.
Memory mapped at address 0x7fb09bb000.
Value at address 0x2520284 (0x7fb09bb284): 0x0
nvidia@tegra-ubuntu:~$ sudo devmem2 0x02530284 b
/dev/mem opened.
Memory mapped at address 0x7f7b4bc000.
Value at address 0x2530284 (0x7f7b4bc284): 0x1
nvidia@tegra-ubuntu:~$ sudo devmem2 0x02540284 b
/dev/mem opened.
Memory mapped at address 0x7f8e1f1000.
Value at address 0x2540284 (0x7f8e1f1284): 0x1
nvidia@tegra-ubuntu:~$ sudo devmem2 0x02550284 b
/dev/mem opened.
Memory mapped at address 0x7fa7e12000.
Value at address 0x2550284 (0x7fa7e12284): 0x1
nvidia@tegra-ubuntu:~$ sudo devmem2 0x02560284 b
/dev/mem opened.
Memory mapped at address 0x7f9bd49000.
Value at address 0x2560284 (0x7f9bd49284): 0x1
nvidia@tegra-ubuntu:~$ sudo devmem2 0x02570284 b
/dev/mem opened.
Memory mapped at address 0x7f8d040000.
Value at address 0x2570284 (0x7f8d040284): 0x2
nvidia@tegra-ubuntu:~$ dmesg | grep pcie
[ 0.257780] GPIO line 459 (pcie-lane2-mux) hogged as output/low
[ 0.260764] iommu: Adding device 10003000.pcie-controller to group 50
[ 7.464245] tegra-pcie 10003000.pcie-controller: 2x1, 1x1, 1x1 configuration
[ 7.474998] tegra-pcie 10003000.pcie-controller: PCIE: Enable power rails
[ 7.485676] tegra-pcie 10003000.pcie-controller: probing port 0, using 2 lanes
[ 7.497771] tegra-pcie 10003000.pcie-controller: probing port 1, using 1 lanes
[ 7.499874] tegra-pcie 10003000.pcie-controller: probing port 2, using 1 lanes
nvidia@tegra-ubuntu:~$ dmesg | grep fragment
node /plugin-manager/soc-prod-a02-fragment match with chip-id A02P
node /plugin-manager/fragment-e3326@0 match with board 3326-*
node /plugin-manager/fragment-p3310-c00-camera match with board >=3489-0000-200
We are using JetPack-L4T-3.2.1.
We made the following changes to the software and dts files in ~/JetPack-L4T-3.2.1/64_TX2/Linux_for_Tegra to change from Lane Mapping Configuration #2 to Configuration #5.
file: p2771-0000.conf.common
ODMDATA=0x2090000
file: ./sources/hardware/nvidia/platform/t18x/quill/kernel-dts/tegra186-quill-p3489-1000-a00-00-base.dts
file: ./sources/hardware/nvidia/platform/t18x/quill/kernel-dts/tegra186-quill-p3310-1000-a00-00-base.dts
xhci@3530000 {
status = "okay";
phys = <&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(2)>,
<&tegra_xusb_padctl TEGRA_PADCTL_PHY_USB3_P(1)>,
<&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(1)>,
<&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(0)>,
<&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(3)>;
phy-names = "utmi-2", "usb3-1", "utmi-1", "utmi-0", "utmi-3";
nvidia,boost_cpu_freq = <800>;
};
pinctrl@3520000 {
status = "okay";
pinctrl-0 = <&tegra_xusb_padctl_pinmux_default>;
pinctrl-1 = <&vbus_en0_sfio_tristate_state>;
pinctrl-2 = <&vbus_en1_sfio_tristate_state>;
pinctrl-3 = <&vbus_en0_sfio_passthrough_state>;
pinctrl-4 = <&vbus_en1_sfio_passthrough_state>;
pinctrl-5 = <&vbus_en0_default_state>;
pinctrl-6 = <&vbus_en1_default_state>;
pinctrl-names = "default",
"vbus_en0_sfio_tristate", "vbus_en1_sfio_tristate",
"vbus_en0_sfio_passthrough", "vbus_en1_sfio_passthrough",
"vbus_en0_default", "vbus_en1_default";
tegra_xusb_padctl_pinmux_default: pinmux {
/* Quill does not support usb3-micro AB */
usb2-micro-AB {
nvidia,lanes = "otg-0";
nvidia,function = "xusb";
nvidia,port-cap = <TEGRA_PADCTL_PORT_OTG_CAP>;
nvidia,oc-pin = <0>;
};
usb2-std-A-port2 {
nvidia,lanes = "otg-1";
nvidia,function = "xusb";
nvidia,port-cap = <TEGRA_PADCTL_PORT_HOST_ONLY>;
nvidia,oc-pin = <1>;
};
usb3-std-A-port2 {
nvidia,lanes = "usb3-0";
nvidia,port-cap = <TEGRA_PADCTL_PORT_HOST_ONLY>;
nvidia,oc-pin = <1>;
status = "disabled";
};
e3325-usb3-std-A-HS {
nvidia,lanes = "otg-2";
nvidia,function = "xusb";
nvidia,port-cap = <TEGRA_PADCTL_PORT_HOST_ONLY>;
status = "disabled";
};
e3325-usb3-std-A-SS {
nvidia,lanes = "usb3-1";
nvidia,port-cap = <TEGRA_PADCTL_PORT_HOST_ONLY>;
status = "okay";
};
};
};
pcie-controller@10003000 {
status = "okay";
pci@1,0 {
nvidia,num-lanes = <2>;
status = "okay";
};
pci@2,0 {
nvidia,num-lanes = <1>;
status = "okay";
};
pci@3,0 {
nvidia,num-lanes = <1>;
status = "okay";
};
};
file: ./sources/hardware/nvidia/platform/t18x/common/kernel-dts/t18x-common-platforms/tegra186-quill-common-p3489-1000-a00.dtsi
file: ./sources/hardware/nvidia/platform/t18x/common/kernel-dts/t18x-common-platforms/tegra186-quill-common-p3310-1000-a00.dtsi
pcie0_lane2_mux {
gpio-hog;
gpios = <TEGRA_MAIN_GPIO(R, 3) 0>;
output-high;
label = “pcie-lane2-mux”;
status = “disabled”;
};
file: tegra186-quill-power-tree-p3310-1000-a00-00.dtsi
file: tegra186-quill-power-tree-p3489-1000-a00-00.dtsi
pinctrl@3520000 {
vbus-0-supply = <&vdd_usb0_5v>;
vbus-1-supply = <&vdd_usb1_5v>;
vbus-2-supply = <&battery_reg>;
vbus-3-supply = <&battery_reg>;
vddio-hsic-supply = <&battery_reg>;
avdd_usb-supply = <&spmic_sd3>;
vclamp_usb-supply = <&spmic_sd2>;
avdd_pll_erefeut-supply = <&spmic_sd2>;
};
file: tegra186-quill-p3489-1000-a00-plugin-manager.dtsi (removed the entire plugin-manager section)
I did not make any other changes to the software.
We designed our custom carrier board for USB Lane Mapping Configuration #5 described in the Tegra Linux Driver Package TX2 Adaptation Guide.
Here is our custom carrier board USB/PCIe pinout.
TX2i Lane TX2i Phy Carrier Board Connector
PEX0Lane4,USB_SS1Lane2 utmi-0 (x2 lanes) M.2 Port on backside of carrier board
PEX2Lane3 utmi-1 (x1 lane) PCIe Port2 on bottom of carrier board
PEX1Lane0 utmi-2 (x1 lane) PCIe Port1 on top of carrier board
PEX_RFULane1 usb3-1 (USB_SS#1) USB3.0 Mux on carrier board (USB/Eth + 3 External USB)
TX2i Pin Carrier Board Pin Name
PEX1_RX-/USB_SS0_RX- H42 PCIe_Port2_Bottom_RXN
PEX1_RX+/USB_SS0_RX+ H41 PCIe_Port2_Bottom_RXP
PEX1_TX-/USB_SS0_TX- E42 PCIe_Port2_Bottom_TXN
PEX1_TX+/USB_SS0_TX+ E41 PCIe_Port2_Bottom_TXP
PEX_RFU_RX- G40 USB3_0_RXN
PEX_RFU_RX+ G39 USB3_0_RXP
PEX_RFU_TX- D40 USB3_0_TXN
PEX_RFU_TX+ D39 USB3_0_TXP
USB_SS1_RX- G43 M_2_Lane1_RXN
USB_SS1_RX+ G42 M_2_Lane1_RXP
USB_SS1_TX- D43 M_2_Lane1_TXN
USB_SS1_TX+ D42 M_2_Lane1_TXP
PEX2_RX- F41 PCIe_Port1_Top_RXN
PEX2_RX+ F40 PCIe_Port1_Top_RXP
PEX2_TX- C41 PCIe_Port1_Top_TXN
PEX2_TX+ C40 PCIe_Port1_Top_TXP
PEX0_RX- H45 M_2_Lane0_RXN
PEX0_RX+ H44 M_2_Lane0_RXP
PEX0_TX- E45 M_2_Lane0_TXN
PEX0_TX+ E44 M_2_Lane0_TXP