I know there are a number of forum posts wit instructions to change the USB lane mappings, but they are hard to follow and it is unclear to me.
I am trying to enable USB lane mapping configuration 3 with the main goal of using a PCI device with PEX1. I followed the example here Jetson/TX2 USB - eLinux.org
I set ODMDATA=0x6090000 in my p2771-0000.conf.common:
# Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
# * Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# * Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# * Neither the name of NVIDIA CORPORATION nor the names of its
# contributors may be used to endorse or promote products derived
# from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
# OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sub_var_token()
{
local var="$1";
local from="$2";
local to="$3";
if [ "${var}" != "" -a "${!var}" != "" ]; then
if [[ "${!var}" =~ "${from}" ]]; then
local val=`echo "${!var}" | sed -e s/${from}/${to}/`;
eval "${var}=${val}";
fi;
fi;
}
# Process fuse version:
#
# Production Fused BD vs non-fused BD::::::
#
# preboot_d15_dev_cr.bin vs. preboot_d15_prod_cr.bin
# mce_mts_d15_dev_cr.bin vs. mce_mts_d15_prod_cr.bin
# mb1_dev.bin vs. mb1_prod.bin
# mb1_recovery_dev.bin vs. mb1_recovery_prod.bin
#
process_fuse_level()
{
local fuselevel="${1}";
local srctoken="_dev";
local trgtoken="_prod";
# fuselevel:
# "fuselevel_unknown"
# "fuselevel_nofuse"
# "fuselevel_production"
#
if [ "${fuselevel}" = "fuselevel_unknown" ]; then
return;
fi;
if [ "${fuselevel}" = "fuselevel_nofuse" ]; then
srctoken="_prod";
trgtoken="_dev";
sub_var_token "WB0BOOT" "warmboot.bin" "warmboot_dev.bin";
else
sub_var_token "WB0BOOT" "warmboot_dev.bin" "warmboot.bin";
fi;
sub_var_token "MTSPREBOOT" "${srctoken}" "${trgtoken}";
sub_var_token "MTS" "${srctoken}" "${trgtoken}";
sub_var_token "MB1FILE" "${srctoken}" "${trgtoken}";
sub_var_token "SOSFILE" "${srctoken}" "${trgtoken}";
}
process_board_version()
{
local board_id="${1}";
local board_version="${2}";
local bdv=${board_version^^};
local bid=${board_id^^};
local uboot_build=500;
local fromfab="-a00";
local tofab="-c03"; # default = C03
local pmicfab="-c00"; # default = C00
local bpfdtbfab="-c00"; # default = C00
local tbcdtbfab="-c03"; # default = C03
local kerndtbfab="-c03"; # default = C03
#ODMDATA=0x1090000; # default = C0X
ODMDATA=0x6090000;
#
# Board version is Alpah-Numeric value.
#
echo "Board ID(${board_id}) version(${board_version}) " >/dev/stderr;
if ! [[ "${bdv}" =~ ^[A-Z0-9][0-9][0-9]$ ]]; then
bdv="${DEFAULT_FAB:-Z99}";
fi;
if [ "${bid}" \= "3313" ]; then
if [ "${bdv}" \= "000" ]; then
# FAB - A00
pmicfab="-c04";
bpfdtbfab="-c04";
else
if [ "${USE_UBOOT}" -eq 1 ]; then
echo "not supported by U-Boot" >/dev/stderr;
exit 1;
fi;
echo -n "Invalid board version(${board_version})." >/dev/stderr;
echo " Using default ODMDATA(${ODMDATA})" >/dev/stderr;
fi;
elif [ "${bid}" \= "3301" ]; then
ODMDATA=0x90000;
uboot_build=000;
tofab="-a00";
pmicfab="-a00";
bpfdtbfab="-a00";
tbcdtbfab="-a00";
kerndtbfab="-a00";
elif [ "${bid}" \= "3489" ]; then
ODMDATA=0x1090000;
tofab="-a00";
pmicfab="-a00";
bpfdtbfab="-a00";
tbcdtbfab="-a00";
kerndtbfab="-a00";
if [ "${bdv}" \< "300" ]; then
bpfdtbfab="-evt";
fi
else
if [ "${bdv}" \< "300" ]; then
# FAB - A02
ODMDATA=0x2090000;
uboot_build=000;
tofab="-a00";
pmicfab="-a00";
bpfdtbfab="-a00";
tbcdtbfab="-a00";
kerndtbfab="-a00";
elif [ "${bdv}" \< "500" ]; then
# FAB - A03..
if [ "${USE_UBOOT}" -eq 1 ]; then
echo "not supported by U-Boot" >/dev/stderr;
exit 1;
fi;
ODMDATA=0x2090000;
uboot_build=000;
tofab="-a00";
pmicfab="-a00";
bpfdtbfab="-a00";
tbcdtbfab="-a00";
kerndtbfab="-a00";
elif [ "${bdv}" \< "800" ]; then
# FAB = b0x
ODMDATA=0x1090000;
tofab="-a00";
pmicfab="-a00";
bpfdtbfab="-a00";
tbcdtbfab="-a00";
kerndtbfab="-a00";
elif [ "${bdv}" \< "900" ]; then
# FAB = c00
tofab="-c00";
pmicfab="-c00";
bpfdtbfab="-c00";
tbcdtbfab="-a00";
kerndtbfab="-a00";
elif [ "${bdv}" \< "A00" ]; then
# FAB = c01
pmicfab="-c01";
bpfdtbfab="-c01";
elif [ "${bdv}" \< "B00" ]; then
# FAB = c02
pmicfab="-c02";
bpfdtbfab="-c01";
elif [ "${bdv}" \< "B01" ]; then
# FAB = c03
pmicfab="-c03";
bpfdtbfab="-c01";
elif [ "${bdv}" \= "B01" -o "${bdv}" \> "B01" ]; then
# FAB = c04
# Treat later VERSIONs as software-compatible.
# Incompatible VERSIONs will require a new entry below.
pmicfab="-c04";
bpfdtbfab="-c04";
else
if [ "${USE_UBOOT}" -eq 1 ]; then
echo "not supported by U-Boot" >/dev/stderr;
exit 1;
fi;
echo -n "Invalid board version(${board_version})." >/dev/stderr;
echo " Using default ODMDATA(${ODMDATA})" >/dev/stderr;
fi;
fi;
sub_var_token "BPFDTB_FILE" "${fromfab}" "${bpfdtbfab}";
sub_var_token "PINMUX_CONFIG" "${fromfab}" "${tofab}";
sub_var_token "PMIC_CONFIG" "${fromfab}" "${pmicfab}";
sub_var_token "PMC_CONFIG" "${fromfab}" "${tofab}";
sub_var_token "PROD_CONFIG" "${fromfab}" "${tofab}";
sub_var_token "BOOTROM_CONFIG" "${fromfab}" "${tofab}";
sub_var_token "TBCDTB_FILE" "${fromfab}" "${tbcdtbfab}";
sub_var_token "DTB_FILE" "${fromfab}" "${kerndtbfab}";
if [ "${USE_UBOOT}" -eq 1 ]; then
DFLT_KERNEL_IMAGE="bootloader/t186ref/p2771-0000/";
DFLT_KERNEL_IMAGE+="${uboot_build}/u-boot.bin";
fi;
}
# Common values and/or defaults across p2771-0000*.conf:
CHIPID=0x18;
EMMC_CFG=flash_l4t_t186.xml;
BOOTPARTSIZE=8388608;
EMMCSIZE=31276924928;
ITS_FILE=;
SYSBOOTFILE=p2771-0000/extlinux.conf;
EMMC_BCT=P3310_A00_8GB_Samsung_8GB_lpddr4_204Mhz_A02_l4t.cfg
DTB_FILE=tegra186-quill-p3310-1000-a00-00-base.dtb;
TBCDTB_FILE=tegra186-quill-p3310-1000-a00-00-base.dtb;
# To configure whether to use U-Boot,
# do either of the following before running flash.sh:
# 1) Set environment variable USE_UBOOT to 0 or 1.
# 2) Edit the line below to set USE_UBOOT to 0 or 1.
if [ -z "${USE_UBOOT}" ]; then
USE_UBOOT=1;
fi;
ROOTFSSIZE=28GiB;
CMDLINE_ADD="console=ttyS0,115200n8 console=tty0 OS=l4t fbcon=map:0 net.ifnames=0";
target_board="t186ref";
ROOT_DEV="mmcblk0p12 ------------ internal eMMC.
sda1 ----------------- external USB devices. (USB memory stick, HDD)
eth0 ----------------- nfsroot via RJ45 Ethernet port.
eth1 ----------------- nfsroot via USB Ethernet interface.";
TEGRABOOT="bootloader/t186ref/nvtboot.bin";
WB0BOOT="bootloader/t186ref/warmboot.bin";
FLASHAPP="bootloader/tegraflash.py";
FLASHER="bootloader/nvtboot_recovery_cpu.bin";
BOOTLOADER="bootloader/nvtboot_cpu.bin";
INITRD="bootloader/l4t_initrd.img";
TBCFILE="bootloader/cboot.bin";
BPFFILE="bootloader/bpmp.bin";
TOSFILE="bootloader/tos.img";
EKSFILE="bootloader/eks.img";
MTSPREBOOT="bootloader/preboot_d15_prod_cr.bin";
MTS="bootloader/mce_mts_d15_prod_cr.bin";
MB1FILE="bootloader/mb1_prod.bin";
SOSFILE="bootloader/mb1_recovery_prod.bin";
MB2BLFILE="bootloader/nvtboot_recovery.bin";
# BCT args:
#
BCT="--sdram_config";
BINSARGS="--bins \"";
DEV_PARAMS="emmc.cfg";
SCR_CONFIG="minimal_scr.cfg";
SCR_COLD_BOOT_CONFIG="mobile_scr.cfg";
MISC_CONFIG="tegra186-mb1-bct-misc-si-l4t.cfg";
PINMUX_CONFIG="tegra186-mb1-bct-pinmux-quill-p3310-1000-a00.cfg";
PMIC_CONFIG="tegra186-mb1-bct-pmic-quill-p3310-1000-a00.cfg";
PMC_CONFIG="tegra186-mb1-bct-pad-quill-p3310-1000-a00.cfg";
PROD_CONFIG="tegra186-mb1-bct-prod-quill-p3310-1000-a00.cfg";
BOOTROM_CONFIG="tegra186-mb1-bct-bootrom-quill-p3310-1000-a00.cfg";
# Default FAB: Force Quill boards without properly programmed EEPROM.
# Values: C01->800, C02->900, C02->A00, C03->B00
#
DEFAULT_FAB="B01";
In tegra186-quill-p3310-1000-a00-plugin-manager.dtsi I commented out fragment-500-pcie-config, fragment-500-xusb-config, and fragment-500-e3325-pcie
/*
* tegra186-quill-p3310-1000-a00-plugin-manager.dtsi: P3310 plugin manager
*
* Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#include "tegra186-soc-prod-plugin-manager.dtsi"
#include "tegra186-odm-data-plugin-manager.dtsi"
#include "tegra186-quill-p3310-1000-300-plugin-manager.dtsi"
/ {
eeprom-manager {
data-size = <0x100>;
boardid-with-revision = <3310>;
boardid-with-config = <3310>;
bus@0 {
i2c-bus = <&gen8_i2c>;
eeprom@0 {
slave-address = <0x50>;
label = "cvm";
};
eeprom@1 {
slave-address = <0x57>;
label = "cvb";
};
};
bus@1 {
i2c-bus = <&gen2_i2c>;
eeprom@0 {
slave-address = <0x51>;
};
};
bus@2 {
i2c-bus = <&gen1_i2c>;
eeprom@0 {
slave-address = <0x50>;
};
};
bus@3 {
i2c-bus = <&cam_i2c>;
eeprom@0 {
slave-address = <0x54>;
label = "cam";
enable-gpio = <2 9>;
};
};
};
plugin-manager {
fragment-devslp@0 {
ids = ">=3310-1000-200";
override@0 {
target = <&{/ahci-sata@3507000}>;
_overlay_ {
gpios = <&spmic 7 0>;
};
};
override@1 {
target = <&{/bpmp_i2c/spmic@3c/pinmux@0}>;
_overlay_ {
pin_gpio7 {
drive-push-pull = <1>;
};
};
};
};
fragment-e3325-xusb {
enable-override-on-all-matches;
ids = "<3310-1000-500";
odm-data = "enable-xusb-on-uphy-lane0";
override@0 {
target = <&tegra_xusb_padctl_pinmux_default>;
_overlay_ {
e3325-usb3-std-A-HS {
status = "okay";
};
e3325-usb3-std-A-SS {
status = "okay";
};
};
};
override@1 {
target = <&{/xhci@3530000}>;
_overlay_ {
phys = <&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(0)>,
<&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(1)>,
<&tegra_xusb_padctl TEGRA_PADCTL_PHY_USB3_P(1)>,
<&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(2)>,
<&tegra_xusb_padctl TEGRA_PADCTL_PHY_USB3_P(0)>;
phy-names = "utmi-0", "utmi-1", "usb3-1", "utmi-2", "usb3-0";
};
};
override@2 {
target = <&tegra_main_gpio>;
_overlay_ {
e3325_sdio_rst {
status = "okay";
};
e3325_lane0_mux {
status = "okay";
};
};
};
override@3 {
target = <&tegra_pcie>;
_overlay_ {
pci@1,0 {
nvidia,num-lanes = <2>;
};
pci@2,0 {
nvidia,num-lanes = <1>;
};
pci@3,0 {
nvidia,num-lanes = <1>;
};
};
};
};
// fragment-500-pcie-config {
// ids = ">=3310-1000-500";
// override@0 {
// target = <&tegra_pcie>;
// _overlay_ {
// pci@1,0 {
// nvidia,num-lanes = <4>;
// };
// pci@2,0 {
// nvidia,num-lanes = <0>;
// };
// pci@3,0 {
// nvidia,num-lanes = <1>;
// };
// };
// };
// };
fragment-comms-a00-chip {
ids = "<3310-1000-500";
override@0 {
target = <&bcm4354>;
_overlay_ {
sdhci-host = <&sdmmc3>;
pwr-retry-cnt = <0>;
interrupt-parent = <&tegra_main_gpio>;
interrupts = <TEGRA_MAIN_GPIO(C, 0) 0x14>;
delete-target-property = "wlan-pwr-gpio";
};
};
override@1 {
target = <&tegra_main_gpio>;
_overlay_ {
wifi-wake-ap {
status = "okay";
gpios = <TEGRA_MAIN_GPIO(C, 0) 0>;
};
wifi-enable {
gpios = <TEGRA_MAIN_GPIO(B, 6) 0>;
};
};
};
override@3 {
target = <&tegra_aon_gpio>;
_overlay_ {
wifi-wake-ap {
status = "disabled";
};
};
};
};
// fragment-500-xusb-config {
// ids = ">=3310-1000-500";
// override@0 {
// target = <&{/xhci@3530000}>;
// _overlay_ {
// phys = <&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(0)>,
// <&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(1)>,
// <&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(2)>,
// <&tegra_xusb_padctl TEGRA_PADCTL_PHY_USB3_P(0)>;
// phy-names = "utmi-0", "utmi-1", "utmi-2", "usb3-0";
// };
// };
// override@1 {
// target = <&tegra_xusb_padctl_pinmux_default>;
// _overlay_ {
// usb3-std-A-port2 {
// nvidia,lanes = "usb3-0";
// };
// e3325-usb3-std-A-HS {
// status = "okay";
// };
// };
// };
// };
// fragment-500-e3325-pcie {
// enable-override-on-all-matches;
// ids = ">=3310-1000-500";
// odm-data = "enable-pcie-on-uphy-lane0";
// override@0 {
// target = <&{/xhci@3530000}>;
// _overlay_ {
// phys = <&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(0)>,
// <&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(1)>,
// <&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(2)>;
// phy-names = "utmi-0", "utmi-1", "utmi-2";
// };
// };
// override@1 {
// target = <&tegra_xusb_padctl_pinmux_default>;
// _overlay_ {
// usb3-std-A-port2 {
// status = "disabled";
// };
// };
// };
// override@2 {
// target = <&tegra_main_gpio>;
// _overlay_ {
// pcie0_lane2_mux {
// status = "okay";
// };
// };
// };
// };
fragment-e3320-dp {
ids = ">=3320-1000-000", ">=3320-1100-000";
override@0 {
target = <&{/host1x}>;
_overlay_ {
nvdisplay@15220000 {
status = "okay";
};
sor {
status = "okay";
dp-display {
status = "okay";
};
};
dpaux@155c0000 {
status = "okay";
};
};
};
};
fragment-p3310-c00-comm {
ids = ">=3310-1000-800";
override@0 {
target = <&{/bluedroid_pm}>;
_overlay_ {
bluedroid_pm,reset-gpio = <&tegra_main_gpio TEGRA_MAIN_GPIO(H, 5) 0>;
};
};
};
fragment-p3310-c00-pmic {
ids = ">=3310-1000-800";
override@0 {
target = <&spmic_ldo6>;
_overlay_ {
maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
};
};
};
fragment-p3310-c01 {
ids = ">=3310-1000-900";
override@0 {
target = <&{/bpmp_i2c/spmic@3c/regulators/ldo6}>;
_overlay_ {
regulator-boot-on;
regulator-always-on;
};
};
override@1 {
target = <&{/bpmp_i2c/spmic@3c/pinmux@0}>;
_overlay_ {
pin_gpio2 {
status = "disabled";
};
pin_gpio3 {
status = "disabled";
};
};
};
};
fragment-p3310-c03 {
ids = ">=3310-1000-B00";
override@1 {
target = <&spmic_ldo8>;
_overlay_ {
regulator-name = "dvdd-pex";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
};
};
override@2 {
target = <&spmic_ldo0>;
_overlay_ {
maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
};
};
override@3 {
target = <&spmic_ldo7>;
_overlay_ {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
};
};
};
};
};
in hardware/nvidia/platform/t18x/quill/kernel-dts/tegra186-quill-p3310-1000-c03-00-base.dts I used the example setup found on elinux
/*
* tegra186-quill-p3310-c03-00-base.dts Quill C03 Board
*
* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#include "tegra186-quill-p3310-1000-a00-00-base.dts"
/ {
nvidia,dtsfilename = __FILE__;
nvidia,dtbbuildtime = __DATE__, __TIME__;
pinmux@2430000 {
common {
gpio_edp2_pp5 {
status = "okay";
};
gpio_edp3_pp6 {
status = "okay";
};
};
};
gpio@2200000 {
sdmmc-wake-support-input {
status = "okay";
};
sdmmc-wake-support-output {
status = "okay";
};
pcie0_lane2_mux {
status = "okay"; //This is for switch from usb3.0 to x1 PCIe on M.2.
};
};
fixed-regulators {
regulator@1 {
gpio = <&tegra_main_gpio TEGRA_MAIN_GPIO(P, 6) 0>;
};
};
sdhci@3400000 {
cd-gpios = <&tegra_main_gpio TEGRA_MAIN_GPIO(P, 5) 0>;
nvidia,cd-wakeup-capable;
};
i2c@3160000 {
ina3221x@40 {
channel@0 {
ti,shunt-resistor-mohm = <10>;
};
channel@1 {
ti,shunt-resistor-mohm = <10>;
};
};
ina3221x@41 {
channel@0 {
ti,shunt-resistor-mohm = <20>;
};
channel@1 {
ti,shunt-resistor-mohm = <10>;
};
channel@2 {
ti,rail-name = "VDD_SYS_DDR";
ti,shunt-resistor-mohm = <10>;
};
};
};
ahci-sata@3507000 {
gpios = <&spmic 7 0>;
};
pcie-controller@10003000 {
pci@1,0 {
nvidia,num-lanes = <1>;
nvidia,disable-clock-request;
status = "okay";
};
pci@2,0 {
nvidia,num-lanes = <1>;
status = "okay";
};
pci@3,0 {
nvidia,num-lanes = <1>;
status = "okay";
};
};
xhci@3530000 {
phys = <&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(0)>,
<&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(1)>,
<&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(2)>,
<&tegra_xusb_padctl TEGRA_PADCTL_PHY_USB3_P(1)>,
<&tegra_xusb_padctl TEGRA_PADCTL_PHY_USB3_P(2)>;
phy-names = "utmi-0", "utmi-1", "utmi-2", "usb3-1", "usb3-2";
};
pinctrl@3520000 {
pinmux {
usb3-std-A-port2 {
nvidia,lanes = "usb3-1";
nvidia,port-cap = <TEGRA_PADCTL_PORT_HOST_ONLY>;
status = "okay";
};
usb3-std-A-port3 {
nvidia,lanes = "usb3-2";
nvidia,port-cap = <TEGRA_PADCTL_PORT_HOST_ONLY>;
status = "okay";
};
e3325-usb3-std-A-HS {
status = "okay"; //This is usb2.0 port on M.2
};
};
};
bluedroid_pm {
bluedroid_pm,reset-gpio = <&tegra_main_gpio TEGRA_MAIN_GPIO(H, 5) 0>;
};
bpmp_i2c {
spmic@3c {
pinmux@0 {
pin_gpio2 {
status = "disabled";
};
pin_gpio3 {
status = "disabled";
};
pin_gpio7 {
drive-push-pull = <1>;
};
};
regulators {
ldo0 {
maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
};
ldo6 {
maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
regulator-boot-on;
regulator-always-on;
};
ldo7 {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
};
ldo8 {
regulator-name = "dvdd-pex";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
};
};
};
};
};
Is there anything else I need to change?
I am trying to use a PCI device on PEX1. So far on my custom carrier board I am not able to get any devices to appear. I get nothing from the output of lspci. Is there a way on the tx2 that I can verify everything is configured correctly for a PCI device on PEX1?
Here is the schematic for my pcie connector
