USB Lane Mapping Instructions

I know there are a number of forum posts wit instructions to change the USB lane mappings, but they are hard to follow and it is unclear to me.

I am trying to enable USB lane mapping configuration 3 with the main goal of using a PCI device with PEX1. I followed the example here https://elinux.org/Jetson/TX2_USB

I set ODMDATA=0x6090000 in my p2771-0000.conf.common:

# Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#  * Redistributions of source code must retain the above copyright
#    notice, this list of conditions and the following disclaimer.
#  * Redistributions in binary form must reproduce the above copyright
#    notice, this list of conditions and the following disclaimer in the
#    documentation and/or other materials provided with the distribution.
#  * Neither the name of NVIDIA CORPORATION nor the names of its
#    contributors may be used to endorse or promote products derived
#    from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
# OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

sub_var_token()
{
	local var="$1";
	local from="$2";
	local to="$3";
	if [ "${var}" != "" -a "${!var}" != "" ]; then
		if [[ "${!var}" =~ "${from}" ]]; then
			local val=`echo "${!var}" | sed -e s/${from}/${to}/`;
			eval "${var}=${val}";
		fi;
	fi;
}

# Process fuse version:
#
# Production Fused BD vs non-fused BD::::::
#
# preboot_d15_dev_cr.bin vs. preboot_d15_prod_cr.bin
# mce_mts_d15_dev_cr.bin vs. mce_mts_d15_prod_cr.bin
# mb1_dev.bin            vs. mb1_prod.bin
# mb1_recovery_dev.bin   vs. mb1_recovery_prod.bin
#
process_fuse_level()
{
	local fuselevel="${1}";
	local srctoken="_dev";
	local trgtoken="_prod";

	# fuselevel:
	#	"fuselevel_unknown"
	#	"fuselevel_nofuse"
	#	"fuselevel_production"
	#
	if [ "${fuselevel}" = "fuselevel_unknown" ]; then
		return;
	fi;
	if [ "${fuselevel}" = "fuselevel_nofuse" ]; then
		srctoken="_prod";
		trgtoken="_dev";
		sub_var_token "WB0BOOT" "warmboot.bin" "warmboot_dev.bin";
	else
		sub_var_token "WB0BOOT" "warmboot_dev.bin" "warmboot.bin";
	fi;
	sub_var_token "MTSPREBOOT" "${srctoken}" "${trgtoken}";
	sub_var_token "MTS"        "${srctoken}" "${trgtoken}";
	sub_var_token "MB1FILE"    "${srctoken}" "${trgtoken}";
	sub_var_token "SOSFILE"    "${srctoken}" "${trgtoken}";
}

process_board_version()
{
	local board_id="${1}";
	local board_version="${2}";
	local bdv=${board_version^^};
	local bid=${board_id^^};
	local uboot_build=500;
	local fromfab="-a00";
	local tofab="-c03";		# default = C03
	local pmicfab="-c00";		# default = C00
	local bpfdtbfab="-c00";		# default = C00
	local tbcdtbfab="-c03";		# default = C03
	local kerndtbfab="-c03";	# default = C03
	#ODMDATA=0x1090000;		# default = C0X
	ODMDATA=0x6090000;

	#
	# Board version is Alpah-Numeric value.
	#
	echo "Board ID(${board_id}) version(${board_version}) " >/dev/stderr;
	if ! [[ "${bdv}" =~ ^[A-Z0-9][0-9][0-9]$ ]]; then
		bdv="${DEFAULT_FAB:-Z99}";
	fi;

	if [ "${bid}" \= "3313" ]; then
		if [ "${bdv}" \= "000" ]; then
			# FAB - A00
			pmicfab="-c04";
			bpfdtbfab="-c04";
		else
			if [ "${USE_UBOOT}" -eq 1 ]; then
				echo "not supported by U-Boot" >/dev/stderr;
				exit 1;
			fi;
			echo -n "Invalid board version(${board_version})." >/dev/stderr;
			echo " Using default ODMDATA(${ODMDATA})" >/dev/stderr;
		fi;
	elif [ "${bid}" \= "3301" ]; then
		ODMDATA=0x90000;
		uboot_build=000;
		tofab="-a00";
		pmicfab="-a00";
		bpfdtbfab="-a00";
		tbcdtbfab="-a00";
		kerndtbfab="-a00";
	elif [ "${bid}" \= "3489" ]; then
		ODMDATA=0x1090000;
		tofab="-a00";
		pmicfab="-a00";
		bpfdtbfab="-a00";
		tbcdtbfab="-a00";
		kerndtbfab="-a00";
		if [ "${bdv}" \< "300" ]; then
			bpfdtbfab="-evt";
		fi
	else
		if [ "${bdv}" \< "300" ]; then
			# FAB - A02
			ODMDATA=0x2090000;
			uboot_build=000;
			tofab="-a00";
			pmicfab="-a00";
			bpfdtbfab="-a00";
			tbcdtbfab="-a00";
			kerndtbfab="-a00";
		elif [ "${bdv}" \< "500" ]; then
			# FAB - A03..
			if [ "${USE_UBOOT}" -eq 1 ]; then
				echo "not supported by U-Boot" >/dev/stderr;
				exit 1;
			fi;
			ODMDATA=0x2090000;
			uboot_build=000;
			tofab="-a00";
			pmicfab="-a00";
			bpfdtbfab="-a00";
			tbcdtbfab="-a00";
			kerndtbfab="-a00";
		elif [ "${bdv}" \< "800" ]; then
			# FAB = b0x
			ODMDATA=0x1090000;
			tofab="-a00";
			pmicfab="-a00";
			bpfdtbfab="-a00";
			tbcdtbfab="-a00";
			kerndtbfab="-a00";
		elif [ "${bdv}" \< "900" ]; then
			# FAB = c00
			tofab="-c00";
			pmicfab="-c00";
			bpfdtbfab="-c00";
			tbcdtbfab="-a00";
			kerndtbfab="-a00";
		elif [ "${bdv}" \< "A00" ]; then
			# FAB = c01
			pmicfab="-c01";
			bpfdtbfab="-c01";
		elif [ "${bdv}" \< "B00" ]; then
			# FAB = c02
			pmicfab="-c02";
			bpfdtbfab="-c01";
		elif [ "${bdv}" \< "B01" ]; then
			# FAB = c03
			pmicfab="-c03";
			bpfdtbfab="-c01";
		elif [ "${bdv}" \= "B01" -o "${bdv}" \> "B01" ]; then
			# FAB = c04
			# Treat later VERSIONs as software-compatible.
			# Incompatible VERSIONs will require a new entry below.
			pmicfab="-c04";
			bpfdtbfab="-c04";
		else
			if [ "${USE_UBOOT}" -eq 1 ]; then
				echo "not supported by U-Boot" >/dev/stderr;
				exit 1;
			fi;
			echo -n "Invalid board version(${board_version})." >/dev/stderr;
			echo " Using default ODMDATA(${ODMDATA})" >/dev/stderr;
		fi;
	fi;

	sub_var_token "BPFDTB_FILE"    "${fromfab}" "${bpfdtbfab}";
	sub_var_token "PINMUX_CONFIG"  "${fromfab}" "${tofab}";
	sub_var_token "PMIC_CONFIG"    "${fromfab}" "${pmicfab}";
	sub_var_token "PMC_CONFIG"     "${fromfab}" "${tofab}";
	sub_var_token "PROD_CONFIG"    "${fromfab}" "${tofab}";
	sub_var_token "BOOTROM_CONFIG" "${fromfab}" "${tofab}";
	sub_var_token "TBCDTB_FILE"    "${fromfab}" "${tbcdtbfab}";
	sub_var_token "DTB_FILE"       "${fromfab}" "${kerndtbfab}";

	if [ "${USE_UBOOT}" -eq 1 ]; then
		DFLT_KERNEL_IMAGE="bootloader/t186ref/p2771-0000/";
		DFLT_KERNEL_IMAGE+="${uboot_build}/u-boot.bin";
	fi;
}

# Common values and/or defaults across p2771-0000*.conf:

CHIPID=0x18;
EMMC_CFG=flash_l4t_t186.xml;
BOOTPARTSIZE=8388608;
EMMCSIZE=31276924928;
ITS_FILE=;
SYSBOOTFILE=p2771-0000/extlinux.conf;
EMMC_BCT=P3310_A00_8GB_Samsung_8GB_lpddr4_204Mhz_A02_l4t.cfg
DTB_FILE=tegra186-quill-p3310-1000-a00-00-base.dtb;
TBCDTB_FILE=tegra186-quill-p3310-1000-a00-00-base.dtb;
# To configure whether to use U-Boot,
# do either of the following before running flash.sh:
# 1) Set environment variable USE_UBOOT to 0 or 1.
# 2) Edit the line below to set USE_UBOOT to 0 or 1.
if [ -z "${USE_UBOOT}" ]; then
	USE_UBOOT=1;
fi;
ROOTFSSIZE=28GiB;
CMDLINE_ADD="console=ttyS0,115200n8 console=tty0 OS=l4t fbcon=map:0 net.ifnames=0";
target_board="t186ref";
ROOT_DEV="mmcblk0p12 ------------ internal eMMC.
        sda1 ----------------- external USB devices. (USB memory stick, HDD)
        eth0 ----------------- nfsroot via RJ45 Ethernet port.
        eth1 ----------------- nfsroot via USB Ethernet interface.";
TEGRABOOT="bootloader/t186ref/nvtboot.bin";
WB0BOOT="bootloader/t186ref/warmboot.bin";
FLASHAPP="bootloader/tegraflash.py";
FLASHER="bootloader/nvtboot_recovery_cpu.bin";
BOOTLOADER="bootloader/nvtboot_cpu.bin";
INITRD="bootloader/l4t_initrd.img";
TBCFILE="bootloader/cboot.bin";
BPFFILE="bootloader/bpmp.bin";
TOSFILE="bootloader/tos.img";
EKSFILE="bootloader/eks.img";
MTSPREBOOT="bootloader/preboot_d15_prod_cr.bin";
MTS="bootloader/mce_mts_d15_prod_cr.bin";
MB1FILE="bootloader/mb1_prod.bin";
SOSFILE="bootloader/mb1_recovery_prod.bin";
MB2BLFILE="bootloader/nvtboot_recovery.bin";

# BCT args:
#
BCT="--sdram_config";
BINSARGS="--bins \"";
DEV_PARAMS="emmc.cfg";
SCR_CONFIG="minimal_scr.cfg";
SCR_COLD_BOOT_CONFIG="mobile_scr.cfg";
MISC_CONFIG="tegra186-mb1-bct-misc-si-l4t.cfg";
PINMUX_CONFIG="tegra186-mb1-bct-pinmux-quill-p3310-1000-a00.cfg";
PMIC_CONFIG="tegra186-mb1-bct-pmic-quill-p3310-1000-a00.cfg";
PMC_CONFIG="tegra186-mb1-bct-pad-quill-p3310-1000-a00.cfg";
PROD_CONFIG="tegra186-mb1-bct-prod-quill-p3310-1000-a00.cfg";
BOOTROM_CONFIG="tegra186-mb1-bct-bootrom-quill-p3310-1000-a00.cfg";

# Default FAB: Force Quill boards without properly programmed EEPROM.
# Values: C01->800, C02->900, C02->A00, C03->B00
#
DEFAULT_FAB="B01";

In tegra186-quill-p3310-1000-a00-plugin-manager.dtsi I commented out fragment-500-pcie-config, fragment-500-xusb-config, and fragment-500-e3325-pcie

/*
 * tegra186-quill-p3310-1000-a00-plugin-manager.dtsi: P3310 plugin manager
 *
 * Copyright (c) 2015-2017, NVIDIA CORPORATION.  All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 */

#include "tegra186-soc-prod-plugin-manager.dtsi"
#include "tegra186-odm-data-plugin-manager.dtsi"
#include "tegra186-quill-p3310-1000-300-plugin-manager.dtsi"

/ {
	eeprom-manager {
		data-size = <0x100>;
		boardid-with-revision = <3310>;
		boardid-with-config = <3310>;
		bus@0 {
			i2c-bus = <&gen8_i2c>;
			eeprom@0 {
				slave-address = <0x50>;
				label = "cvm";
			};
			eeprom@1 {
				slave-address = <0x57>;
				label = "cvb";
			};
		};
		bus@1 {
			i2c-bus = <&gen2_i2c>;
			eeprom@0 {
				slave-address = <0x51>;
			};
		};
		bus@2 {
			i2c-bus = <&gen1_i2c>;
			eeprom@0 {
				slave-address = <0x50>;
			};
		};
		bus@3 {
			i2c-bus = <&cam_i2c>;
			eeprom@0 {
				slave-address = <0x54>;
				label = "cam";
				enable-gpio = <2 9>;
			};
		};
	};
	plugin-manager {
		fragment-devslp@0 {
			ids = ">=3310-1000-200";
			override@0 {
				target = <&{/ahci-sata@3507000}>;
				_overlay_ {
					gpios = <&spmic 7 0>;
				};
			};
			override@1 {
				target = <&{/bpmp_i2c/spmic@3c/pinmux@0}>;
				_overlay_ {
					pin_gpio7 {
						drive-push-pull = <1>;
					};
				};
			};
		};
		fragment-e3325-xusb {
			enable-override-on-all-matches;
			ids = "<3310-1000-500";
			odm-data = "enable-xusb-on-uphy-lane0";
			override@0 {
				target = <&tegra_xusb_padctl_pinmux_default>;
				_overlay_ {
					e3325-usb3-std-A-HS {
						status = "okay";
					};
					e3325-usb3-std-A-SS {
						status = "okay";
					};
				};
			};
			override@1 {
				target = <&{/xhci@3530000}>;
				_overlay_ {
					phys = <&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(0)>,
							<&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(1)>,
							<&tegra_xusb_padctl TEGRA_PADCTL_PHY_USB3_P(1)>,
							<&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(2)>,
							<&tegra_xusb_padctl TEGRA_PADCTL_PHY_USB3_P(0)>;
					phy-names = "utmi-0", "utmi-1", "usb3-1", "utmi-2", "usb3-0";
				};
			};
			override@2 {
				target = <&tegra_main_gpio>;
				_overlay_ {
					e3325_sdio_rst {
						status = "okay";
					};
					e3325_lane0_mux {
						status = "okay";
					};
				};
			};
			override@3 {
				target = <&tegra_pcie>;
				_overlay_ {
					pci@1,0 {
						nvidia,num-lanes = <2>;
					};
					pci@2,0 {
						nvidia,num-lanes = <1>;
					};
					pci@3,0 {
						nvidia,num-lanes = <1>;
					};
				};
			};
		};
		// fragment-500-pcie-config {
		// 	ids = ">=3310-1000-500";
		// 	override@0 {
		// 		target = <&tegra_pcie>;
		// 		_overlay_ {
		// 			pci@1,0 {
		// 				nvidia,num-lanes = <4>;
		// 			};
		// 			pci@2,0 {
		// 				nvidia,num-lanes = <0>;
		// 			};
		// 			pci@3,0 {
		// 				nvidia,num-lanes = <1>;
		// 			};
		// 		};
		// 	};
		// };
		fragment-comms-a00-chip {
			ids = "<3310-1000-500";
			override@0 {
				target = <&bcm4354>;
				_overlay_ {
					sdhci-host = <&sdmmc3>;
					pwr-retry-cnt = <0>;
					interrupt-parent = <&tegra_main_gpio>;
					interrupts = <TEGRA_MAIN_GPIO(C, 0) 0x14>;
					delete-target-property = "wlan-pwr-gpio";
				};
			};
			override@1 {
				target = <&tegra_main_gpio>;
				_overlay_ {
					wifi-wake-ap {
						status = "okay";
						gpios = <TEGRA_MAIN_GPIO(C, 0) 0>;
					};

					wifi-enable {
						gpios = <TEGRA_MAIN_GPIO(B, 6) 0>;
					};
				};
			};

			override@3 {
				target = <&tegra_aon_gpio>;
				_overlay_ {
					wifi-wake-ap {
						status = "disabled";
					};
				};
			};
		};
		// fragment-500-xusb-config {
		// 	ids = ">=3310-1000-500";
		// 	override@0 {
		// 		target = <&{/xhci@3530000}>;
		// 		_overlay_ {
		// 			phys = <&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(0)>,
		// 				<&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(1)>,
		// 				<&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(2)>,
		// 				<&tegra_xusb_padctl TEGRA_PADCTL_PHY_USB3_P(0)>;
		// 			phy-names = "utmi-0", "utmi-1", "utmi-2", "usb3-0";
		// 		};
		// 	};
		// 	override@1 {
		// 		target = <&tegra_xusb_padctl_pinmux_default>;
		// 		_overlay_ {
		// 			usb3-std-A-port2 {
		// 				nvidia,lanes = "usb3-0";
		// 			};
		// 			e3325-usb3-std-A-HS {
		// 				status = "okay";
		// 			};
		// 		};
		// 	};
		// };
		// fragment-500-e3325-pcie {
		// 	enable-override-on-all-matches;
		// 	ids = ">=3310-1000-500";
		// 	odm-data = "enable-pcie-on-uphy-lane0";
		// 	override@0 {
		// 		target = <&{/xhci@3530000}>;
		// 		_overlay_ {
		// 			phys = <&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(0)>,
		// 				<&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(1)>,
		// 				<&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(2)>;
		// 			phy-names = "utmi-0", "utmi-1", "utmi-2";
		// 		};
		// 	};
		// 	override@1 {
		// 		target = <&tegra_xusb_padctl_pinmux_default>;
		// 		_overlay_ {
		// 			usb3-std-A-port2 {
		// 				status = "disabled";
		// 			};
		// 		};
		// 	};

		// 	override@2 {
		// 		target = <&tegra_main_gpio>;
		// 		_overlay_ {
		// 			pcie0_lane2_mux {
		// 				status = "okay";
		// 			};
		// 		};
		// 	};
		// };

		fragment-e3320-dp {
			ids = ">=3320-1000-000", ">=3320-1100-000";
			override@0 {
				target = <&{/host1x}>;
				_overlay_ {
					nvdisplay@15220000 {
						status = "okay";
					};
					sor {
						status = "okay";
						dp-display {
							status = "okay";
						};
					};
					dpaux@155c0000 {
						status = "okay";
					};
				};
			};
		};

		fragment-p3310-c00-comm {
			ids = ">=3310-1000-800";
			override@0 {
				target = <&{/bluedroid_pm}>;
				_overlay_ {
					bluedroid_pm,reset-gpio = <&tegra_main_gpio TEGRA_MAIN_GPIO(H, 5) 0>;
				};
			};
		};

		fragment-p3310-c00-pmic {
			ids = ">=3310-1000-800";
			override@0 {
				target = <&spmic_ldo6>;
				_overlay_ {
					maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
				};
			};
		};

		fragment-p3310-c01 {
			ids = ">=3310-1000-900";
			override@0 {
				target = <&{/bpmp_i2c/spmic@3c/regulators/ldo6}>;
				_overlay_ {
					regulator-boot-on;
					regulator-always-on;
				};
			};
			override@1 {
				target = <&{/bpmp_i2c/spmic@3c/pinmux@0}>;
				_overlay_ {
					pin_gpio2 {
						status = "disabled";
					};
					pin_gpio3 {
						status = "disabled";
					};
				};
			};
		};

		fragment-p3310-c03 {
			ids = ">=3310-1000-B00";

			override@1 {
				target = <&spmic_ldo8>;
				_overlay_ {
					regulator-name = "dvdd-pex";
					regulator-min-microvolt = <1000000>;
					regulator-max-microvolt = <1000000>;
				};
			};

			override@2 {
				target = <&spmic_ldo0>;
				_overlay_ {
					maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
				};
			};

			override@3 {
				target = <&spmic_ldo7>;
				_overlay_ {
					regulator-min-microvolt = <1000000>;
					regulator-max-microvolt = <1000000>;
				};
			};
		};
	};
};

in hardware/nvidia/platform/t18x/quill/kernel-dts/tegra186-quill-p3310-1000-c03-00-base.dts I used the example setup found on elinux

/*
 * tegra186-quill-p3310-c03-00-base.dts Quill C03 Board
 *
 * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 */

#include "tegra186-quill-p3310-1000-a00-00-base.dts"

/ {
	nvidia,dtsfilename = __FILE__;
	nvidia,dtbbuildtime = __DATE__, __TIME__;

	pinmux@2430000 {
		common {
			gpio_edp2_pp5 {
				status = "okay";
			};

			gpio_edp3_pp6 {
				status = "okay";
			};
		};
	};

   gpio@2200000 {
		sdmmc-wake-support-input {
			status = "okay";
		};

		sdmmc-wake-support-output {
			status = "okay";
		};
		pcie0_lane2_mux {
			status = "okay"; //This is for switch from usb3.0 to x1 PCIe  on M.2.
		};
	};

	fixed-regulators {
		regulator@1 {
			gpio = <&tegra_main_gpio TEGRA_MAIN_GPIO(P, 6) 0>;
                };
	};

	sdhci@3400000 {
		cd-gpios = <&tegra_main_gpio TEGRA_MAIN_GPIO(P, 5) 0>;
		nvidia,cd-wakeup-capable;
	};

	i2c@3160000 {
		ina3221x@40 {
			channel@0 {
				ti,shunt-resistor-mohm = <10>;
			};
			channel@1 {
				ti,shunt-resistor-mohm = <10>;
			};
		};
		ina3221x@41 {
			channel@0 {
				ti,shunt-resistor-mohm = <20>;
			};
			channel@1 {
				ti,shunt-resistor-mohm = <10>;
			};
			channel@2 {
				ti,rail-name = "VDD_SYS_DDR";
				ti,shunt-resistor-mohm = <10>;
			};
		};
	};

	ahci-sata@3507000 {
		gpios = <&spmic 7 0>;
	};

	pcie-controller@10003000 {
		pci@1,0 {
			nvidia,num-lanes = <1>;
			nvidia,disable-clock-request;
			status = "okay";
		};
		pci@2,0 {
			nvidia,num-lanes = <1>;
			status = "okay";
		};
		pci@3,0 {
			nvidia,num-lanes = <1>;
			status = "okay";
		};
	};

    xhci@3530000 {
		phys = <&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(0)>,
			<&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(1)>,
			<&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(2)>,
			<&tegra_xusb_padctl TEGRA_PADCTL_PHY_USB3_P(1)>,
			<&tegra_xusb_padctl TEGRA_PADCTL_PHY_USB3_P(2)>;
		phy-names = "utmi-0", "utmi-1", "utmi-2", "usb3-1", "usb3-2";
	};

	pinctrl@3520000 {
	    pinmux {
		usb3-std-A-port2 {
			nvidia,lanes = "usb3-1";
			nvidia,port-cap = <TEGRA_PADCTL_PORT_HOST_ONLY>;
			status = "okay";
		};
		usb3-std-A-port3 {
			nvidia,lanes = "usb3-2";
			nvidia,port-cap = <TEGRA_PADCTL_PORT_HOST_ONLY>;
			status = "okay";
		};
		e3325-usb3-std-A-HS {
                    status = "okay"; //This is usb2.0 port on M.2
			};
		};
	};

       bluedroid_pm {
		bluedroid_pm,reset-gpio = <&tegra_main_gpio TEGRA_MAIN_GPIO(H, 5) 0>;
        };

	bpmp_i2c {
		spmic@3c {
			pinmux@0 {
				pin_gpio2 {
					status = "disabled";
				};
				pin_gpio3 {
					status = "disabled";
				};
				pin_gpio7 {
					drive-push-pull = <1>;
				};
			};

			regulators {
				ldo0 {
					maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
				};

				ldo6 {
					maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
					regulator-boot-on;
					regulator-always-on;
				};

				ldo7 {
					regulator-min-microvolt = <1000000>;
					regulator-max-microvolt = <1000000>;
				};

				ldo8 {
					regulator-name = "dvdd-pex";
					regulator-min-microvolt = <1000000>;
					regulator-max-microvolt = <1000000>;
				};
			};
		};
	};
};

Is there anything else I need to change?

I am trying to use a PCI device on PEX1. So far on my custom carrier board I am not able to get any devices to appear. I get nothing from the output of lspci. Is there a way on the tx2 that I can verify everything is configured correctly for a PCI device on PEX1?

Here is the schematic for my pcie connector


Hi,
Do you apply change to t18x-common-platforms/tegra186-quill-power-tree-p3310-1000-a00-00.dtsi ?
https://elinux.org/Jetson/TX2_USB#Patching_the_DTS

Yes I followed the instructions and here is my t18x-common-platforms/tegra186-quill-power-tree-p3310-1000-a00-00.dtsi

/*
 * Copyright (c) 2015-2017, NVIDIA CORPORATION.  All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 */

#include "tegra186-quill-spmic-p3310-1000-a00-00.dtsi"
#include "tegra186-cvb-prod-p2597-b00-p3310-1000-a00-00.dtsi"

/ {

	fixed-regulators {
		vdd_1v8_ap: regulator@101 {
			compatible = "regulator-fixed";
			reg = <101>;
			regulator-name = "vdd-1v8-ap";
			regulator-min-microvolt = <1800000>;
			regulator-max-microvolt = <1800000>;
			regulator-always-on;
			regulator-boot-on;
		};
	};


	ether_qos@2490000 {
		vddio_sys_enet_bias-supply = <&spmic_sd2>;
		vddio_enet-supply = <&spmic_sd3>;
		phy_vdd_1v8-supply = <&spmic_sd2>;
		phy_ovdd_rgmii-supply = <&spmic_sd3>;
		phy_pllvdd-supply = <&spmic_sd1>;
	};

	host1x {
		nvdisplay@15200000 {
			avdd_lcd-supply = <&en_avdd_disp_3v3>;
			dvdd_lcd-supply = <&en_vdd_disp_1v8>;
			avdd_dsi_csi-supply = <&spmic_sd1>;
			outp-supply = <&vpp_lcd>;
			outn-supply = <&vmm_lcd>;
			vdd_lcd_bl-supply = <&battery_reg>;
			vdd_lcd_bl_en-supply = <&vdd_bl_en>;
			/* added hdmi for testing in head 0 */
			avdd_hdmi-supply = <&spmic_ldo7>;
			avdd_hdmi_pll-supply = <&spmic_sd2>;
			vdd_hdmi_5v0-supply = <&vdd_hdmi>;
		};
		nvdisplay@15210000 {
			avdd_hdmi-supply = <&spmic_ldo7>;
			avdd_hdmi_pll-supply = <&spmic_sd2>;
			vdd_hdmi_5v0-supply = <&vdd_hdmi>;
		};
		nvdisplay@15220000 {
			vdd-dp-pwr-supply = <&battery_reg>;
			avdd-dp-pll-supply = <&battery_reg>;
			vdd-edp-sec-mode-supply = <&battery_reg>;
			vdd-dp-pad-supply = <&battery_reg>;
			vdd_hdmi_5v0-supply = <&battery_reg>;
		};
		vi@15700000 {
			avdd_dsi_csi-supply = <&spmic_sd1>;
		};
		nvcsi@150c0000 {
			nvidia,csi_regulator = "avdd_dsi_csi";
		};
	};

	sdhci@3460000 {
		vqmmc-supply = <&spmic_sd2>;
		vmmc-supply = <&spmic_sd3>;
	};

	sdhci@3440000 {
		vqmmc-supply = <&spmic_ldo5>;
		vmmc-supply = <&spmic_sd2>;
	};

	sdhci@3420000 {
		vqmmc-supply = <&spmic_sd2>;
		vmmc-supply = <&spmic_sd3>;
	};

	sdhci@3400000 {
		vqmmc-supply = <&spmic_ldo3>;
		vmmc-supply = <&en_vdd_sdcard1>;
	};

	xhci@3530000 {
		avddio_usb-supply = <&spmic_sd3>;
		avdd_pll_utmip-supply = <&spmic_sd2>;
		hvdd_usb-supply =  <&spmic_sd2>;
	};

	xudc@3550000 {
		avdd-usb-supply = <&spmic_sd3>;
	};

	pinctrl@3520000 {
		vbus-0-supply = <&vdd_usb0_5v>;
		vbus-1-supply = <&vdd_usb1_5v>;
		// vbus-2-supply = <&vdd_usb2_5v>;
		vbus-2-supply = <&battery_reg>;
		vbus-3-supply = <&battery_reg>;
		vddio-hsic-supply = <&battery_reg>;
		avdd_usb-supply = <&spmic_sd3>;
		vclamp_usb-supply = <&spmic_sd2>;
		avdd_pll_erefeut-supply = <&spmic_sd2>;
	};

	spi@c260000 {
		spi-touch-sharp19x12@0 {
			avdd-supply = <&en_vdd_ts_hv_3v3>;
			dvdd-supply = <&en_vdd_ts_1v8>;
		};
	};

	pcie-controller@10003000 {
		vddio-pexctl-aud-supply = <&spmic_sd2>;
	};

	pmc-iopower {
		vddio-sys-supply = <&vdd_1v8_ap>;
		vddio-uart-supply = <&vdd_1v8_ap>;
		vddio-conn-supply = <&vdd_1v8_ap>;
		vddio-edp-supply = <&vdd_1v8_ap>;
		vddio-pex-ctrl-supply = <&vdd_1v8_ap>;
		vddio-audio-supply = <&vdd_1v8_ap>;
		vddio-ufs-supply = <&vdd_1v8_ap>;
		vddio-ddr0-supply = <&spmic_sd0>;
		vddio-ddr1-supply = <&spmic_sd0>;
		vddio-mipi-bias-supply = <&spmic_sd1>;
		vddio-cam-supply = <&vdd_1v8_ap>;
		vddio-sdmmc4-supply = <&vdd_1v8_ap>;
		vddio-sdmmc1-hv-supply = <&spmic_ldo3>;
		vddio-audio-hv-supply = <&vdd_1v8_ap>;
		vddio-dbg-supply = <&vdd_1v8_ap>;
		vddio-spi-supply = <&vdd_1v8_ap>;
		vddio-ao-supply = <&vdd_1v8_ap>;
		vddio-ao-hv-supply = <&spmic_ldo2>;
		vddio-dmic-hv-supply =  <&vdd_1v8_ap>;
		vddio-sdmmc2-hv-supply = <&spmic_sd3>;
		vddio-sdmmc3-hv-supply =  <&spmic_ldo5>;
	};

	i2c@c250000 {
		tegra_tmp451: temp-sensor@4c {
			vdd-supply = <&vdd_1v8_ap>;
		};
	};

	pwm-fan {
		vdd-fan-supply = <&vdd_fan>;
	};

	bluedroid_pm {
		avdd-supply = <&battery_reg>;
		dvdd-supply = <&spmic_sd2>;
	};

	bpmp_i2c {
		spmic@3c {
			pinmux@0 {

				pin_gpio1 {
					maxim,active-fps-power-up-slot = <1>;
					maxim,active-fps-power-down-slot = <3>;
				};

				pin_gpio2 {
					maxim,active-fps-power-up-slot = <7>;
					maxim,active-fps-power-down-slot = <1>;
				};

				pin_gpio3 {
					maxim,active-fps-power-up-slot = <1>;
					maxim,active-fps-power-down-slot = <7>;
				};
			};

			regulators {
				sd0 {
					maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
					maxim,active-fps-power-up-slot = <5>;
					maxim,active-fps-power-down-slot = <2>;
					regulator-enable-ramp-delay = <278>;
					regulator-disable-ramp-delay = <153000>;
					maxim,ramp-rate-setting = <27500>;
					regulator-ramp-delay = <3930>;
				};

				sd1 {
					maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
					maxim,active-fps-power-up-slot = <3>;
					maxim,active-fps-power-down-slot = <1>;
					regulator-enable-ramp-delay = <211>;
					regulator-disable-ramp-delay = <40000>;
					maxim,ramp-rate-setting = <27500>;
					regulator-ramp-delay = <5500>;
				};

				sd2 {
					maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
					maxim,active-fps-power-up-slot = <0>;
					maxim,active-fps-power-down-slot = <7>;
					regulator-enable-ramp-delay = <4000>;
					regulator-disable-ramp-delay = <21000>;
					maxim,ramp-rate-setting = <27500>;
					regulator-ramp-delay = <450>;
				};

				sd3 {
					maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
					maxim,active-fps-power-up-slot = <6>;
					maxim,active-fps-power-down-slot = <1>;
					regulator-enable-ramp-delay = <574>;
					regulator-disable-ramp-delay = <40000>;
					maxim,ramp-rate-setting = <27500>;
					regulator-ramp-delay = <5500>;
				};

				ldo0 {
					maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
					maxim,active-fps-power-up-slot = <3>;
					maxim,active-fps-power-down-slot = <3>;
					maxim,ramp-rate-setting = <100000>;
					regulator-ramp-delay = <100000>;
				};

				ldo1 {
					maxim,ramp-rate-setting = <100000>;
					regulator-ramp-delay = <100000>;
				};

				ldo2 {
					maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
					maxim,active-fps-power-up-slot = <6>;
					maxim,active-fps-power-down-slot = <1>;
					regulator-enable-ramp-delay = <152>;
					regulator-disable-ramp-delay = <14000>;
					maxim,ramp-rate-setting = <100000>;
					regulator-ramp-delay = <20000>;
				};

				ldo3 {
					maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
					maxim,active-fps-power-up-slot = <0>;
					maxim,active-fps-power-down-slot = <7>;
					regulator-enable-ramp-delay = <160>;
					regulator-disable-ramp-delay = <16000>;
					maxim,ramp-rate-setting = <5000>;
					regulator-ramp-delay = <1000>;
				};

				ldo4 {
					maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
					maxim,active-fps-power-up-slot = <1>;
					maxim,active-fps-power-down-slot = <7>;
					regulator-enable-ramp-delay = <26>;
					regulator-disable-ramp-delay = <1650>;
					maxim,ramp-rate-setting = <100000>;
					regulator-ramp-delay = <33000>;
				};

				ldo5 {
					maxim,active-fps-power-up-slot = <0>;
					maxim,active-fps-power-down-slot = <7>;
					regulator-enable-ramp-delay = <309>;
					regulator-disable-ramp-delay = <16000>;
					maxim,ramp-rate-setting = <5000>;
					regulator-ramp-delay = <526>;
				};

				ldo6 {
					maxim,ramp-rate-setting = <100000>;
					regulator-ramp-delay = <100000>;
				};

				ldo7 {
					maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
					maxim,active-fps-power-up-slot = <4>;
					maxim,active-fps-power-down-slot = <1>;
					regulator-enable-ramp-delay = <95>;
					regulator-disable-ramp-delay = <15000>;
					maxim,ramp-rate-setting = <100000>;
					regulator-ramp-delay = <10000>;
				};

			};
		};
	};

	fixed-regulators {
		regulator@1 {
			regulator-enable-ramp-delay = <1120>;
			regulator-disable-ramp-delay = <16500>;
		};

		regulator@2 {
			regulator-enable-ramp-delay = <108>;
			regulator-disable-ramp-delay = <1200>;
		};

		regulator@3 {
			regulator-enable-ramp-delay = <745>;
			regulator-disable-ramp-delay = <74000>;
		};

		regulator@4 {
			regulator-enable-ramp-delay = <945>;
			regulator-disable-ramp-delay = <2650>;
		};

		regulator@5 {
			regulator-enable-ramp-delay = <800>;
			regulator-disable-ramp-delay = <13000>;
		};

		regulator@6 {
			regulator-enable-ramp-delay = <173>;
			regulator-disable-ramp-delay = <13000>;
		};

		regulator@7 {
			regulator-enable-ramp-delay = <245>;
			regulator-disable-ramp-delay = <43000>;
		};

		regulator@8 {
			regulator-enable-ramp-delay = <216>;
			regulator-disable-ramp-delay = <43000>;
		};

		regulator@10 {
			regulator-enable-ramp-delay = <178>;
			regulator-disable-ramp-delay = <10000>;
		};

		regulator@11 {
			regulator-enable-ramp-delay = <5000>;
			regulator-disable-ramp-delay = <87000>;
		};
	};
};

PLease check if your new device tree is applied via xxd:
https://devtalk.nvidia.com/default/topic/1043022/jetson-tx2/tx2-set-device-trees-usb-lane-mapping-to-configuration-4/post/5294931/#5294931

That change seems to be in effect.

xxd /proc/device-tree/pinctrl@3520000/vbus-2-supply
00000000: 0000 001a

Is there a way to check that the lane mappings are correct for config 3 / PCI on PEX1?

Please refer to below link:
https://devtalk.nvidia.com/default/topic/1023160/jetson-tx2/tx2-using-pcix1-instead-of-usb3-default-config-1-/post/5208073/#5208073
It shows tips to check device tree and registers.

Here is my output from the post you referenced

xxd /proc/device-tree/xhci@3530000/phy-names
00000000: 7574 6d69 2d30 0075 746d 692d 3100 7574  utmi-0.utmi-1.ut
00000010: 6d69 2d32 0075 7362 332d 3100 7573 6233  mi-2.usb3-1.usb3
00000020: 2d32 00                                  -2.
ll /proc/device-tree/pcie-controller@10003000/
total 0
drwxr-xr-x   6 root root   0 May  6 05:42 ./
drwxr-xr-x 195 root root   0 Feb 11 16:28 ../
-r--r--r--   1 root root   4 May  6 05:42 #address-cells
-r--r--r--   1 root root   8 May  6 05:42 bus-range
-r--r--r--   1 root root  15 May  6 05:42 clock-names
-r--r--r--   1 root root  24 May  6 05:42 clocks
-r--r--r--   1 root root  21 May  6 05:42 compatible
-r--r--r--   1 root root   4 May  6 05:42 device_type
-r--r--r--   1 root root   4 May  6 05:42 #interrupt-cells
-r--r--r--   1 root root  32 May  6 05:42 interrupt-map
-r--r--r--   1 root root  16 May  6 05:42 interrupt-map-mask
-r--r--r--   1 root root   9 May  6 05:42 interrupt-names
-r--r--r--   1 root root  24 May  6 05:42 interrupts
-r--r--r--   1 root root   4 May  6 05:42 linux,phandle
-r--r--r--   1 root root  16 May  6 05:42 name
drwxr-xr-x   2 root root   0 May  6 05:42 pci@1,0/
drwxr-xr-x   2 root root   0 May  6 05:42 pci@2,0/
drwxr-xr-x   2 root root   0 May  6 05:42 pci@3,0/
-r--r--r--   1 root root   4 May  6 05:42 phandle
-r--r--r--   1 root root   4 May  6 05:42 power-domains
drwxr-xr-x   3 root root   0 May  6 05:42 prod-settings/
-r--r--r--   1 root root 168 May  6 05:42 ranges
-r--r--r--   1 root root  48 May  6 05:42 reg
-r--r--r--   1 root root  12 May  6 05:42 reg-names
-r--r--r--   1 root root  15 May  6 05:42 reset-names
-r--r--r--   1 root root  24 May  6 05:42 resets
-r--r--r--   1 root root   4 May  6 05:42 #size-cells
-r--r--r--   1 root root   5 May  6 05:42 status
-r--r--r--   1 root root   4 May  6 05:42 #stream-id-cells
-r--r--r--   1 root root   4 May  6 05:42 vddio-pexctl-aud-supply
ll /proc/device-tree/pinctrl@3520000/pinmux/
total 0
drwxr-xr-x 8 root root 0 May  6 05:43 ./
drwxr-xr-x 4 root root 0 May  6 05:41 ../
drwxr-xr-x 2 root root 0 May  6 05:43 e3325-usb3-std-A-HS/
drwxr-xr-x 2 root root 0 May  6 05:43 e3325-usb3-std-A-SS/
-r--r--r-- 1 root root 4 May  6 05:43 linux,phandle
-r--r--r-- 1 root root 7 May  6 05:43 name
-r--r--r-- 1 root root 4 May  6 05:43 phandle
drwxr-xr-x 2 root root 0 May  6 05:43 usb2-micro-AB/
drwxr-xr-x 2 root root 0 May  6 05:43 usb2-std-A-port2/
drwxr-xr-x 2 root root 0 May  6 05:43 usb3-std-A-port2/
drwxr-xr-x 2 root root 0 May  6 05:43 usb3-std-A-port3/

reading bytes with devmem2 here is my output

Value at address 0x2520284 (0x7f98938284): 0x1
Value at address 0x2530284 (0x7fa7896284): 0x0
Value at address 0x2540284 (0x7f8c21f284): 0x0
Value at address 0x2550284 (0x7f8923c284): 0x1
Value at address 0x2560284 (0x7f8f036284): 0x1
Value at address 0x2560284 (0x7f8f036284): 0x1

Does this look correct for Config 3 as explained here https://elinux.org/Jetson/TX2_USB? This should get PCIe on PEX1, correct?

Hi,
Do you follow adaptation guide to do:

• To switch USB_SS0 to PEX1, configure QSPI_IO2 as follows: 
 
pcie0_lane2_mux {     gpio-hog;
     gpios = <TEGRA_MAIN_GPIO(R, 3) 0>;
     output-low;
     label = "pcie-lane2-mux";
 -    status = "disabled";
 +    status = "okay";
 };

Besides, do USB_SS#1, USB_SS#2 work? Do you see any error about PCIe and USB in boot log?

The adaptation guide does not specify where I am supposed to find QSPI_IO2. searching through the source I found a match to the text in hardware/nvidia/platform/t18x/common/kernel-dts/t18x-common-platforms/tegra186-quill-common-p3310-1000-a00.dtsi. After editing this file and recompiling the device tree it now works.

What DaneLLL posted was just copied from adaptation guide page 13. Please check if you are reading a wrong adaptation guide (old version?).

I found that in the adaptation guide. From the guide I just wasn’t clear on where in the source to make that change. Maybe I missed something.

thank you for all your help.