It does not work.
The phenomenon is that it first turns to a low level and then turns to a high level after a short period of time
After reviewing similar posts, I realized that this may be related to Drive 1, as I saw the engineer’s suggestion for Drive 0.
The problem is that I need to configure GPIO before entering the system to properly initialize the display (GPO2 is the pin that controls display switching), and I want it to output a high level during the bootloader phase like Pinmux. What should I do?
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Based on the provided context, I understand that you are experiencing an issue with a custom Jetson Orin NX 8GB board, where a GPIO pin (GPIO2/GPIO3_PP06) is not behaving as expected. The pin is set as an output and is supposed to drive a high level, but instead, it first goes low and then high after a short period.
After reviewing similar posts, you suspect that this issue might be related to the drive strength of the GPIO pin, specifically the “Drive 1” setting. You want to configure the GPIO pin to output a high level during the bootloader phase, similar to how Pinmux settings work.
To address this issue, I recommend the following steps:
Verify the Pinmux setting: Check the Pinmux setting for the GPIO2/GPIO3_PP06 pin to ensure it is configured correctly. You can use the Jetson AGX Orin pinmux spreadsheet to verify the setting.
Check the GPIO configuration: Review the GPIO configuration for the pin to ensure it is set as an output and the drive strength is set to “Drive 0” (not “Drive 1”). You can use the GPIO tools to dynamically change the GPIO pin settings.
Use the kernel debugfs: Utilize the kernel debugfs feature to debug the GPIO pin. This will allow you to access the GPIO pin’s configuration and settings during the bootloader phase.
Modify the device tree: If necessary, modify the device tree to configure the GPIO pin’s drive strength to “Drive 0” during the bootloader phase. This will ensure that the pin outputs a high level as expected.
Test the configuration: After making the necessary changes, test the GPIO pin’s behavior to ensure it outputs a high level during the bootloader phase.
In comparison to other issues mentioned in the context, this issue seems to be related to the GPIO configuration and Pinmux settings, rather than a kernel issue like the AGX Orin GPIO issue or a PCIe issue like the Lan7430 issue.
Additionally, the Jetson Orin NX Boot Process procedure mentions that the Boot ROM programs the on-chip I/O controllers to access the secondary boot device (QSPI). This might be relevant to your issue, as the GPIO configuration might need to be set before the system enters the bootloader phase.
By following these steps, you should be able to resolve the issue and configure the GPIO pin to output a high level during the bootloader phase.
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