We control GPIOs on Jetson Orin NX (Jetpack 6.1) for a buzzer and found two issues:
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When a GPIO output is set high, physically touching the GPIO pin with a multimeter probe causes the output to drop to low unexpectedly.
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Without the buzzer’s VCC connected, the GPIO toggles high and low as expected. However, when the buzzer’s VCC (3.3V) is connected, setting the GPIO output low causes a brief low pulse but the output quickly returns to high. Using gpioset --mode=wait 0 105=1 (GPIO01) or Python RPi.GPIO GPIO.output(29, GPIO.LOW)keeps the buzzer active, but oscilloscope shows rapid voltage fluctuations.
What could cause these behaviors, and how can we configure the GPIO to ensure stable GPIO output?
Thanks.
Hi @juihung_weng,
I find this gpio behavior very interesting. At face value, unstable gpio behavior suggests to me either an issue in gpio configuration or a hardware issue. Just a few questions to get a better sense of the issue:
- Are you using a devkit or a custom board?
- Have you tested gpios with
/sys/class/gpio and do you see the same behavior? (Perhaps this guide can help with that.)
- What is your pinmux configuration?
Regards,
Francis Guindon
Embedded SW Engineer at RidgeRun
Contact us: support@ridgerun.com
Developers wiki: https://developer.ridgerun.com/
Website: http://www.ridgerun.com/
Hi Francis,
We’re using a devkit. We haven’t tested the GPIOs using the sysfs interface yet, but we’ll do that once we’re back in the office and share the results. We set the pinmux dynamically using sudo busybox devmem 0x02430068 w 0x004 to configure the GPIO01 as output.
Thanks.
Hi Francis,
We’ve checked the GPIO sysfs interface, but the GPIO nodes are not available. According to
Jetson Orin NX and Nano Series — NVIDIA Jetson Linux Developer Guide, starting with JetPack 6, the sysfs interface has been deprecated.
We also suspect the issue may be related to insufficient drive strength. Is there a register we can access via devmem to configure the GPIO drive strength directly? If so, could you point us to the relevant documentation or register map for reference?
Thanks.
Hi juihung_weng,
Are you using the devkit or custom board for Orin NX?
Have you applied the patch from 40hdr - SPI1 gpio padctl register bit[10] effect by gpiod tools in JP6 - #20 by KevinFFF before controlling GPIO with JP6.1?
Hi Kevin,
We are using a devkit. We haven’t applied any patches, so far, we’re using the default image downloaded from NVIDIA’s site. Would applying this patch potentially resolve the GPIO issues we’re seeing?
Thanks.
Yes, this patch is used to fix the known issue we found to control GPIO in JP6.
If bit 10 is set, then it would not work as Output GPIO as expected.
Hi Kevin,
We have applied the patch.
The pin state no longer changes when touched with a multimeter, and using gpioset without the --mode option can now hold the output value.
However, our second issue still remains: the GPIO output does not stay low when connected to a buzzer with VCC(3.3V) connected. The GPIO is expected to stay high by default and remain low after we set it low. However, it fluctuates between high and low. Could this be caused by weak drive strength or misconfiguration? (We configured the pinmux with sudo busybox devmem 0x02430068 w 0x004)
Thanks.
Hi Kevin,
Thank you for the clarification. Regarding the link you shared, it seems it does not describe a standard or confirmed way to adjust GPIO drive strength.
Could you clarify how to properly modify the drive strength of a specific GPIO pin—either through device tree configuration or using a runtime method like devmem? If there’s official documentation or register references for this, that would be greatly appreciated.
Thanks.
Please refer to the document that it indicates To support driving either of these load types, an additional buffer/transistor/FET may be required..
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