Hardware vDPA offloading


I am interested in the vDPA techniques, but there are some confusing things while I am trying to understand. (https://docs.nvidia.com/networking/pages/viewpage.action?pageId=39279792#OVSOffloadUsingASAP²Direct-hwvdpa)

Here are my questions:

  1. (H/W offloading data path) vDPA separates data path and vendor specific control path. In the hardware vDPA offloading with qemu, how packets are delivered from NIC to VM?

  2. (H/W offloading control path) How does the control path change once the H/W offloading is enabled?

  3. Is DPDK necessary? I mean, is DPDK theoretically unavoidable for hardware offloaded vDPA?

Any material or paper is fine.


Hi bk-2,

Thanks for posting your inquiry to the NVIDIA Developer Forums.

1). Regarding offloading path with qemu, data appears to be limited: https://www.qemu.org/docs/master/interop/vhost-vdpa.html. As qemu is community-driven software, we recommend engaging the qemu development community for better understanding.

2). On the link you referenced, in the overview section, the following statement is made:

"The traditional ASAP2 hardware data plane is built over SR-IOV virtual functions (VFs), so that the VF is passed through directly to the VM, with the Mellanox driver running within the VM. An alternate approach that is also supported is vDPA (vhost Data Path Acceleration). vDPA allows the connection to the VM to be established using VirtIO, so that the data-plane is built between the SR-IOV VF and the standard VirtIO driver within the VM, while the control-plane is managed on the host by the vDPA application. "

3). As documented for our solutions, DPDK is a requirement. Other vendors / solutions may have other methods of implementation, but implementation of vDPA without DPDK is currently an unsupported configuration for
our drivers and hardware. That’s not to say ‘it definitely can’t ever be done’, but at current this is a requirement for MLNX_OFED and our adapters.

Hope that helps clarify things.

NVIDIA Enterprise Experience

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