Our camera is sending RAW8 double wide data type and we’re able to receive the frames through the NVCSI/VI block with the following video format settings:
TEGRA_VIDEO_FORMAT(RAW8, 8, SGRBG8_1X8, 1, 1, T_R8, RAW8, SGRBG8, "GRGR.. BGBG.."),
By doubling the width size to 3840 with RAW8 data type, we can receive the image through the NVCSI/VI block correctly. The image looks good.
We would like the VI block to merge the 2x RAW8 and swap the bytes for us, however. The TRM describes a register that I think should work for us (VI_CH_n_PIXFMT_WIDE_).
I made these changes here but it has NOT worked yet:
desc->ch_cfg.pixfmt_wide_enable = 1;
desc->ch_cfg.pixfmt_wide_endian = 1;
With the bits set above, and 2x RAW8 merged, I’d expect a T_R16 from the VI5 block. Is this correct?
We want to then tell the V4L2 driver to expect a SGRBG16_1X16 from the table below. The assumption is that the VI merged the 2x RAW8 into a RAW16 and now the VI is going to DMA it in T_R16 format. Is this correct?
TEGRA_VIDEO_FORMAT(RAW16, 16, SGRBG16_1X16, 2, 1, T_R16, RAW16, SGRBG16, "GRGR.. BGBG.."),
Do I understand the logic correct?
Setting the bits above didn’t work for us.