Hello
The spec of TX1 says that the PCIe is Gen2.
But, we run the test tool, the RX of PCIe is about 1.9GB/s.
So, we have two questions to ask
- Does the PCIe of TX1 only support Gen2?
- How to check the status of PCIe port?(Gen1/Gen2/Gen3)
Thanks
lspci is the tool for looking at PCIe. TX1 is capable of Gen. 2, so PCIe devices will run at Gen. 1 or Gen. 2, depending on signal quality and device capability (Gen. 2 devices are backwards compatible to also run at Gen. 1 speeds, and will do so if either the PCIe slot only supports Gen. 1, or if signal quality causes throttling back to Gen. 1).
If you see a device on PCIe via “lspci”, then you can use verbose output (requires sudo) to see details. Each device listed in the plain “lspci” output has an identifier on the left of the format “##:##.#”. You can use the “-s” option to limit response to this. An example verbose output for “01:00.0” is:
sudo lspci -s "01:00.0" -vvv
Typically you could search within the output for “GT/s” to see various transfer rates. 5GT/s is Gen. 2, 2.5GT/s is Gen. 1. “LnkCap” is a capability of the highest rating of that link; “LnkSta” entries are “status” of actual current operating speeds.
Thanks for your reply.
We connect PEX8732 Gen3 in the Jetson TX1
The information of lspci is as follows:
03:00.0 Bridge: PLX Technology, Inc. PEX 8732 32-lane, 8-Port PCI Express Gen 3 (8.0 GT/s) Switch (rev ca)
Subsystem: PLX Technology, Inc. PEX 8732 32-lane, 8-Port PCI Express Gen 3 (8.0 GT/s) Switch
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx-
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- SERR- <PERR- INTx-
Latency: 0, Cache Line Size: 64 bytes
Interrupt: pin A routed to IRQ 130
Region 0: Memory at 13000000 (32-bit, non-prefetchable)
Region 2: Memory at 20000000 (64-bit, prefetchable)
Capabilities: [40] Power Management version 3
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [48] MSI: Enable- Count=1/8 Maskable+ 64bit+
Address: 0000000000000000 Data: 0000
Masking: 00000000 Pending: 00000000
Capabilities: [68] Express (v2) Endpoint, MSI 00
DevCap: MaxPayload 2048 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited
ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset-
DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+
MaxPayload 128 bytes, MaxReadReq 128 bytes
DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
LnkCap: Port #8, Speed 8GT/s, Width x16, ASPM L0s L1, Exit Latency L0s <2us, L1 <4us
ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+
LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk-
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
LnkSta: Speed 2.5GT/s, Width x0, TrErr- Train- SlotClk- DLActive- BWMgmt- ABWMgmt-
DevCap2: Completion Timeout: Not Supported, TimeoutDis-, LTR-, OBFF Not Supported
DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled
LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis-
Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
Compliance De-emphasis: -6dB
LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1-
EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
Capabilities: [c8] Vendor Specific Information: Len=00 <?>
Capabilities: [100 v1] Device Serial Number ca-87-00-10-b5-df-0e-00
Capabilities: [fb4 v1] Advanced Error Reporting
UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-
CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
AERCap: First Error Pointer: 1f, GenCap+ CGenEn- ChkCap+ ChkEn-
Capabilities: [148 v1] Virtual Channel
Caps: LPEVC=0 RefClk=100ns PATEntryBits=1
Arb: Fixed- WRR32- WRR64- WRR128-
Ctrl: ArbSelect=Fixed
Status: InProgress-
VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-
Arb: Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256-
Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff
Status: NegoPending+ InProgress-
Capabilities: [c34 v1] Vendor Specific Information: ID=0003 Rev=0 Len=078 <?>
Capabilities: [b70 v1] Vendor Specific Information: ID=0001 Rev=0 Len=010 <?>
→ We can see that PEX8732 is recognized as GEN3 device. But, as you say that TX1 is support PCIe Gen2, if we insert the PEX8732(GEN3) in the TX1 PCIe slot (GEN2), will the speed of PEX8732 will be limited to Gen2?
And would you share us the test pattern that HW team can use to check the TX1 PCIe speed?
The 8GT/s (giga transfers/sec per channel) would only be possible when running gen. 3 hardware on gen. 3 slots. Had this throttled back to gen. 2 for compatibility, 5GT/s would be possible, and never faster. It appears that your card has throttled all the way back to gen. 1 speeds (2.5GT/s). The most you will get under these circumstances is 2.5GT/s per channel.
I do not know how much you know about PCIe already, forgive me if I am interpreting what you are asking incorrectly…
In general there is an “eye” pattern which can be viewed to see signal quality (I don’t think any specific data for the pattern would matter). Measuring at PCIe 2 speeds I think a scope with 12GS/sec (an oscilloscope sample rate which is extremely fast and expensive) is needed; measuring PCIe 3 data lanes for quality probably works at 12GS/s, but 30GS/s is recommended.
Here is a good video on eye patterns:
[url]#141: What is an Eye Pattern on an Oscilloscope - A Tutorial - YouTube
Here are five videos from Agilent (they make good test equipment) on the topic:
[url]Video 1 of 5: PCI EXPRESS® 3.0 Introduction and Overview - YouTube
[url]Video 2 of 5: PCI EXPRESS® 3.0 Design Challenges - YouTube
[url]Video 3 of 5: PCI EXPRESS® 3.0 De-emphasis - YouTube
[url]Video 4 of 5: PCI EXPRESS® 3.0 Transmitter Testing - YouTube
[url]Video 5 of 5: PCI EXPRESS® 3.0 Receiver Testing - YouTube
TX1 supports only Gen-1 and Gen-2 speeds.
Line “PLX Technology, Inc. PEX 8732 32-lane, 8-Port PCI Express Gen 3 (8.0 GT/s) Switch (rev ca)” you are seeing in lspci output is framed by lspci tool using its data base (file pci.ids usually located @ /usr/share/misc/pci.ids ) to give a verbose interpretation of the device based on its Vendor-ID and Device-ID.
Current link speed can be found out using entries of ‘LnkSta’ (short form for Link Status) in lspci verbose (-vvvv) output.