TX2 USB lane map config #1 Fail

yi-chia.lan · February 20, 2019, 8:59am

Hi ,
Due to use customize board with PCIe x4 + x1 config , we did some modify on device tree file.
After device tree setup, and we bring up carrier board and check register status,
we can get PCIE x4 device, but can not recognize PCIe x1 device on our PCB board.

Did any thing we miss to change on device tree ??

xhci@3530000 {
		status = "okay";
		phys = <&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(0)>,
			<&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(2)>,
			<&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(1)>;
		phy-names = "utmi-0", "utmi-2" , "utmi-1";
		nvidia,boost_cpu_freq = <800>;
	};

	pinctrl@3520000 {
		status = "okay";
		pinctrl-0 = <&tegra_xusb_padctl_pinmux_default>;
		pinctrl-1 = <&vbus_en0_sfio_tristate_state>;
		pinctrl-2 = <&vbus_en1_sfio_tristate_state>;
		pinctrl-3 = <&vbus_en0_sfio_passthrough_state>;
		pinctrl-4 = <&vbus_en1_sfio_passthrough_state>;
		pinctrl-5 = <&vbus_en0_default_state>;
		pinctrl-6 = <&vbus_en1_default_state>;
		pinctrl-names = "default",
			"vbus_en0_sfio_tristate", "vbus_en1_sfio_tristate",
			"vbus_en0_sfio_passthrough", "vbus_en1_sfio_passthrough",
			"vbus_en0_default", "vbus_en1_default";
		tegra_xusb_padctl_pinmux_default: pinmux {
			/* Quill does not support usb3-micro AB */
			usb2-micro-AB {
				nvidia,lanes = "otg-0";
				nvidia,function = "xusb";
				nvidia,port-cap = <TEGRA_PADCTL_PORT_OTG_CAP>;
				//nvidia,oc-pin = <0>;
				status = "okay";
			};
			usb2-std-A-port0 {
				nvidia,lanes = "otg-2";
				nvidia,function = "xusb";
				nvidia,port-cap = <TEGRA_PADCTL_PORT_HOST_ONLY>;
				nvidia,oc-pin = <0>;
				status = "okay";
			};
			usb2-std-A-port1 {
				nvidia,lanes = "otg-1";
				nvidia,function = "xusb";
				nvidia,port-cap = <TEGRA_PADCTL_PORT_HOST_ONLY>;
				nvidia,oc-pin = <1>;
				status = "okay";
			};			
		};
	};
	pcie-controller@10003000 {
		status = "okay";
		pci@1,0 {
			nvidia,num-lanes = <4>;
			status = "okay";
		};
		pci@2,0 {
			nvidia,num-lanes = <0>;   
			status = "disabled";
		};
		pci@3,0 {
			nvidia,num-lanes = <1>;
			status = "okay";
		};
	};

        gpio@2200000 {
		sdmmc-wake-support-input {
			status = "okay";
		};

		sdmmc-wake-support-output {
			status = "okay";
		};
		
		pcie0_lane2_mux {
			status = "okay";
		};
	};

kernel dmesg :

nvidia@tegra-ubuntu:~$ dmesg | grep pcie
[    0.228922] GPIO line 459 (pcie-lane2-mux) hogged as output/low
[    0.232291] iommu: Adding device 10003000.pcie-controller to group 49
[    6.281432] tegra-pcie 10003000.pcie-controller: 4x1, 1x1 configuration
[    6.290380] tegra-pcie 10003000.pcie-controller: PCIE: Enable power rails
[    6.298778] tegra-pcie 10003000.pcie-controller: probing port 0, using 4 lanes
[    6.309608] tegra-pcie 10003000.pcie-controller: probing port 2, using 1 lanes
[    6.759740] tegra-pcie 10003000.pcie-controller: link 0 down, retrying
[    7.169784] tegra-pcie 10003000.pcie-controller: link 0 down, retrying
[    7.571730] tegra-pcie 10003000.pcie-controller: link 0 down, retrying
[    7.573758] tegra-pcie 10003000.pcie-controller: link 0 down, ignoring
[    7.973756] tegra-pcie 10003000.pcie-controller: link 2 down, retrying
[    8.415745] tegra-pcie 10003000.pcie-controller: link 2 down, retrying
[    8.827764] tegra-pcie 10003000.pcie-controller: link 2 down, retrying
[    8.861818] tegra-pcie 10003000.pcie-controller: link 2 down, ignoring
[    8.868384] tegra-pcie 10003000.pcie-controller: PCIE: no end points detected
[    8.875984] tegra-pcie 10003000.pcie-controller: PCIE: Disable power rails

ODMDATA = 0x90000

UPHY register value:
Value at address 0x2520284 (0x7fb6a02284): 0x1
Value at address 0x2530284 (0x7f9246e284): 0x1
Value at address 0x2540284 (0x7f7a4be284): 0x1
Value at address 0x2550284 (0x7f7c892284): 0x1
Value at address 0x2560284 (0x7f86c2c284): 0x1
Value at address 0x2570284 (0x7fa813d284): 0x2

tegra186-quill-p3310-1000-c03-00-base.zip (37.1 KB)

WayneWWW · February 21, 2019, 6:31am

Please set

pcie0_lane2_mux {
			status = "okay"; //This is for switch from usb3.0 to x1 PCIe  on M.2.
		};

yi-chia.lan · February 21, 2019, 6:40am

Hi WayneWWW,

We do set pcie0_lane2_mux = okay in device tree.

gpio@2200000 {
sdmmc-wake-support-input {
status = “okay”;
};

	sdmmc-wake-support-output {
		status = "okay";
	};
	
	pcie0_lane2_mux {
		status = "okay";
	};
};

WayneWWW · February 21, 2019, 7:24am

Could you also share the full dmesg?

yi-chia.lan · February 21, 2019, 7:31am

Hi WayneWWW,

My kernel log as attached.
TX2_USB_config_1_kernel_log.txt (69.8 KB)

WayneWWW · February 21, 2019, 7:44am

I doubt if this is hardware issue. Could you verify your dtb on our devkit?

The pcie x1 on devkit is the M.2 E key slot. If even devkit cannot detect the card, please check if any usb node under pinctrl@3520000 is occupied the uphy.

yi-chia.lan · February 21, 2019, 7:52am

Hi WayneWWW,

We were tried to config usb lane map as #5 (2x1 , 1x2) to verify if it is hardware issue, and PEX1 (Lane 0) can detect PCIe device.

Due to this test, we think it may not a hardware problem???

Regards

WayneWWW · February 21, 2019, 8:23am

Do you mean if you use 2x 1-lane pcie config, your port can work?

Are you sure the working one is PEX1 but not PEX2?

yi-chia.lan · February 21, 2019, 8:33am

Hi WayneWWW,

Our x1 PCIE pins connect to B45.B46.H41.H42.E41.E42
And, when lane map set to config #5, PCIE device on B45.B46.H41.H42.E41.E42 detect well.
Is it right pin for PEX1 x1 function???

WayneWWW · February 21, 2019, 8:59am

It looks correct. Could you get any clue by comparing your device tree between config #5 and config #1?

yi-chia.lan · February 21, 2019, 9:47am

Hi WayneWWW,

We only modify ODMDATA and pcie <2><1><1> to <4><0><1> config #5 and config #1.
No other differs.

WayneWWW · February 21, 2019, 10:11am

Could you share the dts instead of dtb?

yi-chia.lan · February 21, 2019, 10:14am

Hi WayneWWW,
DTS file as attached.

hardware.7z (168 KB)

yi-chia.lan · February 27, 2019, 12:35am

Hi,

Any update ?

Regards

WayneWWW · February 27, 2019, 2:25am

I don’t see any error in glance. There are test methods for you.

If you have nvidia devkit, please flash your device tree onto it.
If you don’t have devkit, please use default device tree from jetpack with ODM data changing to 0x90000 to flash you board.

USB may have some problem for both case but what we need to check here is PCIe only.
Please share if any of these method successfully work.

yi-chia.lan · February 27, 2019, 3:30am

Hi WayneWWW,

If you don’t have devkit, please use default device tree from jetpack with ODM data changing to 0x90000 to flash you board.

==> kernel log as attached. USB function seems no problem.

krnlog_devkit_dtb_on_customize_board_with_ODM_0x90000.txt (91.4 KB)

WayneWWW · February 27, 2019, 3:50am

Why should we care about USB? Aren’t we checking PCIe?
Is PCIe on port 2 also working?

yi-chia.lan · February 27, 2019, 3:53am

Hi WayneeWWW,

PCIe device only working on port 0. not card detect on port 2.

Regards

WayneWWW · February 27, 2019, 3:56am

Then I would say please check your hardware design.

This device tree from Jetpack should have no problem and we’ve verified on devkit.

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TX2 USB lane map config #1 Fail

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