Sorry, I did not provide all info.
I’m using 28.1RC and will port to 28.1 release. I followed the platform adaptation and bring up guide and don’t see any changes between 27.1 and 28.1.
I see cfg files are already changed in 28.1RC from 27.1.
I’ve made changes entries for USB in DT and ODMDATA is set as ODMDATA=0x2090000; I’ve all USB working properly. I also find all PCIe working but I don’t get the extra lane that the config#5 should provide.
I’ve a few questions
Does PCIe DT entries look correct? I don’t see info about these in the guide.
What else do I need in cfg files?
Is config#5 verified?
Should I try these in 28.1 release?
Following is DT entries for USB
xudc@3550000 {
status = “okay”;
phys = <&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(0)>;
phy-names = “usb2”;
/dvdd-pex-supply = <&spmic_ldo8>;
dvdd-pex-pll-supply = <&spmic_ldo8>;/
};
xhci@3530000 {
status = "okay";
phys = <&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(0)>,
<&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(1)>,
<&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(2)>,
<&tegra_xusb_padctl TEGRA_PADCTL_PHY_USB3_P(1)>;
phy-names = "utmi-0", "utmi-1", "utmi-2", "usb3-1";
};
pinctrl@3520000 {
status = "okay";
vbus-2-supply = <&battery_reg>;
/*dvdd_pex-supply = <&spmic_ldo8>;*/
pinctrl-0 = <&tegra_xusb_padctl_pinmux_default>;
/*pinctrl-1 = <&vbus_en0_sfio_tristate_state>;
pinctrl-2 = <&vbus_en1_sfio_tristate_state>;
pinctrl-3 = <&vbus_en0_sfio_passthrough_state>;
pinctrl-4 = <&vbus_en1_sfio_passthrough_state>;
pinctrl-5 = <&vbus_en0_default_state>;
pinctrl-6 = <&vbus_en1_default_state>;*/
pinctrl-names = "default",
"vbus_en0_sfio_tristate", "vbus_en1_sfio_tristate",
"vbus_en0_sfio_passthrough", "vbus_en1_sfio_passthrough",
"vbus_en0_default", "vbus_en1_default";
tegra_xusb_padctl_pinmux_default: pinmux {
/* Quill does not support usb3-micro AB */
usb2-micro-AB {
nvidia,lanes = "otg-0";
nvidia,function = "xusb";
nvidia,port-cap = <TEGRA_PADCTL_PORT_OTG_CAP>;
nvidia,oc-pin = <0>;
status = "okay";
};
usb2-std-A-port2 {
nvidia,lanes = "otg-1";
nvidia,function = "xusb";
nvidia,port-cap = <TEGRA_PADCTL_PORT_HOST_ONLY>;
nvidia,oc-pin = <1>;
status = "okay";
};
e3325-usb3-std-A-HS {
nvidia,lanes = "otg-2";
nvidia,function = "xusb";
nvidia,port-cap = <TEGRA_PADCTL_PORT_HOST_ONLY>;
status = "okay";
};
usb3-std-A-port2 {
nvidia,lanes = "usb3-0";
nvidia,port-cap = <TEGRA_PADCTL_PORT_HOST_ONLY>;
status = "disabled";
};
e3325-usb3-std-A-SS {
nvidia,lanes = "usb3-1";
nvidia,port-cap = <TEGRA_PADCTL_PORT_HOST_ONLY>;
status = "okay";
};
};
};