Hi.
I have designed custom carrier board implementing 6-th lane mapping configuration referenced in Jetson TX2 OEM Product Design Guide. I have followed all the steps from Platform Adaptation and Bring-up Guide and but I am unable to register any additional USB ports (both 2.0 and 3.0). I have also read numerous threads regarding USB lane mapping on this forum, but none of those solutions worked for me.
I have disabled plugin-manager and I am sure that my modifications affect the system - I can enable/disable “otg-0” and “usb3-0” ports or switch OTG capability, my changes are also present in /proc/device-tree and decompiled dtb.
According to kernel log PCI seems to be configured correctly (2-1-1), but I haven’t checked it with any device yet.
I have set ODMDATA accordingly, verified it using devmem2, included bootloader .cfg files and reflashed entire MMC.
Jetson module is attached to devkit, currently my method of verification are kernel logs examination and lsusb -t.
Fragment of tegra186-quill-p3310-1000-a00-00-base:
xhci@3530000 {
status = "okay";
phys = <&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(0)>,
<&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(1)>,
<&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(2)>,
<&tegra_xusb_padctl TEGRA_PADCTL_PHY_USB3_P(0)>,
<&tegra_xusb_padctl TEGRA_PADCTL_PHY_USB3_P(1)>;
phy-names = "utmi-0", "utmi-1", "utmi-2", "usb3-0", "usb3-1";
nvidia,boost_cpu_freq = <800>;
};
pinctrl@3520000 {
status = "okay";
pinctrl-0 = <&tegra_xusb_padctl_pinmux_default>;
pinctrl-1 = <&vbus_en0_sfio_tristate_state>;
pinctrl-2 = <&vbus_en1_sfio_tristate_state>;
pinctrl-3 = <&vbus_en0_sfio_passthrough_state>;
pinctrl-4 = <&vbus_en1_sfio_passthrough_state>;
pinctrl-5 = <&vbus_en0_default_state>;
pinctrl-6 = <&vbus_en1_default_state>;
pinctrl-names = "default",
"vbus_en0_sfio_tristate", "vbus_en1_sfio_tristate",
"vbus_en0_sfio_passthrough", "vbus_en1_sfio_passthrough",
"vbus_en0_default", "vbus_en1_default";
tegra_xusb_padctl_pinmux_default: pinmux {
/* Quill does not support usb3-micro AB */
port0-usb2 {
status = "okay";
nvidia,lanes = "otg-0";
nvidia,function = "xusb";
nvidia,port-cap = <TEGRA_PADCTL_PORT_OTG_CAP>;
nvidia,oc-pin = <0>;
};
port0-usb3 {
status = "okay";
nvidia,lanes = "usb3-0";
nvidia,port-cap = <TEGRA_PADCTL_PORT_OTG_CAP>;
};
port1-usb2 {
status = "okay";
nvidia,lanes = "otg-1";
nvidia,function = "xusb";
nvidia,port-cap = <TEGRA_PADCTL_PORT_HOST_ONLY>;
nvidia,oc-pin = <1>;
};
port1-usb3 {
status = "okay";
nvidia,lanes = "usb3-1";
nvidia,port-cap = <TEGRA_PADCTL_PORT_HOST_ONLY>;
};
port3-usb2 {
status = "okay";
nvidia,lanes = "otg-2";
nvidia,function = "xusb";
nvidia,port-cap = <TEGRA_PADCTL_PORT_HOST_ONLY>;
};
};
};
I have removed redundant nodes from tegra186-quill-p3310-1000-c03-00-base that would override this modifications.
By the way, including dtsi files generated by Jetson TX2 Generic Customer Pinmux Template in main DTS file causes system to freeze right after boot - boot serial console is disabled and not re-enabled afterwards, so I can’t tell what is happening. My only modifications were PEX line muxing.
GPIO dtsi contains some unexisting macros, but I believe it is not important in my case.
I am using Jetpack 3.2 release (L4T 28.2).
I might miss some important step and would really appreciate some help.