Jetson TX2 enable USB 3.0 OTG

Hello,

I am developing custom kernel for our custom carrier board using L4T_32.5.

I want to use 2 USB 3.0 ports.

The first one is using the pins A38, A39, F43, F44, C43, C44, A18.

The second one is using the pins B40, B39, G43, G42, D42, D43, A17, A36.

I don’t want to lose the OTG of the second USB port.

The first one is working fine.

The second one is not working, it only works as high speed port (usb 2.0)

I am very unsure of how to modify the kernel tree to indicate the configuration of the custom carrier board.

Thank you.

Hi,

The real helpful information is the board schematic … I really don’t have any answer if you just share some pins here…

Hello Wayne,

2ndUSB30.pdf (70.7 KB)

In the pdf file you can see the schematics of the USB 3.0 connector.
For this connector we have:

Tx0N – D43
Tx0P – D44
Rx0N – G43
Rx0P – G44

Thank you

please refer to the adaptation guide document of your l4t version.

Hello Wayne,

So far I have seen a few things.

This manual has the following table:

If I understand it, those are all the available configurations for the USB, PCI Express and SATA. That means that if I want 2 USB 3.0 I have to use configuration 3 or 6.

In our hardware design, we have created an USB 3.0 using USB_SS#2 and USB_SS#0 but that configuration is not available in the table. The configuration that is similar to the one that we have is 4 which has 3 USB 3.0 and maybe we can just don’t use the USB_SS#1.

I have done modifications in the file hardware/nvidia/platform/t18x/quill/kernel-dts/tegra186-quill-p3489-0888-a00-00-base.dts

To disable the PCI Express I have try this:

    pcie-controller@10003000 {
		//status = "okay";
        status = "disabled";
		/*
		pci@1,0 {
            nvidia,num-lanes = <4>;
            nvidia,disable-clock-request;
			status = "okay";
		};
        pci@2,0 {
            nvidia,num-lanes = <0>;
			status = "disabled";
        };
        pci@3,0 {
            nvidia,num-lanes = <1>;
			status = "okay";
		};
		*/
    };

I think that’s how I have to disable PCI Express pins and then the pins will be used as USB 3.0

Then to enable the 3 USB 3.0 I have added this:

         . . . 
        xusb_padctl@3520000 {

         . . . 

            ports {

                 . . . 

			usb3-1{
				nvidia,usb2-companion = <2>;
				status = "okay";
			};
			usb3-2 {
				nvidia,usb2-companion = <0>;
				status = "okay";
				nvidia,oc-pin = <0>;
			};	

And then added the ports in the phys list:

	xhci@3530000 {
		phys = <&{/xusb_padctl@3520000/pads/usb2/lanes/usb2-0}>,
			   <&{/xusb_padctl@3520000/pads/usb3/lanes/usb3-2}>,
			   <&{/xusb_padctl@3520000/pads/usb2/lanes/usb2-1}>,
			   <&{/xusb_padctl@3520000/pads/usb3/lanes/usb3-0}>,
			   <&{/xusb_padctl@3520000/pads/usb2/lanes/usb2-2}>,
			   <&{/xusb_padctl@3520000/pads/usb3/lanes/usb3-1}>;
		phy-names = "usb2-0", "usb3-2", "usb2-1", "usb3-0", "usb2-2", "usb3-1";
		status = "okay";
	};

But when I connect a USB 3.0 camera to the port the dmesg information shows a high-speed camera

[   62.414780] usb 1-1: new high-speed USB device number 3 using tegra-xusb
[   62.437493] usb 1-1: New USB device found, idVendor=2560, idProduct=c1d0
[   62.437529] usb 1-1: New USB device strings: Mfr=1, Product=2, SerialNumber=3
[   62.437551] usb 1-1: Product: See3CAM_CU130
[   62.437565] usb 1-1: Manufacturer: e-con systems
[   62.437579] usb 1-1: SerialNumber: 3D168B02
[   62.450119] hid-generic 0003:2560:C1D0.0001: hidraw0: USB HID v1.11 Device [e-con systems See3CAM_CU130] on usb-3530000.xhci-1/input2
[   62.484421] uvcvideo: Found UVC 1.00 device See3CAM_CU130 (2560:c1d0)

I know the camera is USB 3.0 because when I connect it to the other port the dmesg information shows a super-speed camera

[   78.863345] usb 2-1: new SuperSpeed USB device number 2 using tegra-xusb
[   78.884152] usb 2-1: LPM exit latency is zeroed, disabling LPM.
[   78.886256] usb 2-1: New USB device found, idVendor=2560, idProduct=c1d0
[   78.886285] usb 2-1: New USB device strings: Mfr=1, Product=2, SerialNumber=3
[   78.886308] usb 2-1: Product: See3CAM_CU130
[   78.886321] usb 2-1: Manufacturer: e-con systems
[   78.886337] usb 2-1: SerialNumber: 3D168B02
[   78.895045] uvcvideo: Found UVC 1.00 device See3CAM_CU130 (2560:c1d0)

I can see that the USB3.0 port that works is the one that is the same as the development kit.

Please can you clarify if the configuration we have designed is possible to use?
if not, configuring the kernel tree as configuration 4 of the table is a possible solution for our case?
How should I modify the kernel tree to configure the PCIe ports to be used as USB SS and not PCIe?

Thank you.

Hi,

First question here. Is this jetson TX2, TX2i, TX2-4GB or TX2-NX?

Second question, which jetpack release are you using?

Hello Wayne,

We are using:
Jetson TX2-4GB
L4T 32.5
Jetpack 4.5

For config #4, you need to set pcie lane to 2,1,1 (no reason behind this, just need to set it) and disabled those lanes you are not using.

Also, you need to modify the “ODMDATA” to match your UPHY lane mapping. This is in your board config where you use it to flash. For TX2 series, should be p2771-0000.conf.common.

Hello Wayne,

Than you for the reply about the P2771-0000.conf.common.

With the change that you mention, when I flash the TX2 I can see that the PCIe lanes 0 to 2 are configured as USB.

ls -la /proc/device-tree/chosen/plugin-manager/odm-data/
total 0
drwxr-xr-x 2 root root 0 ene 28 16:59 .
drwxr-xr-x 6 root root 0 ene 28 16:58 ..
-r--r--r-- 1 root root 4 ene 28 16:58 android-build
-r--r--r-- 1 root root 4 ene 28 16:58 disable-pmic-wdt
-r--r--r-- 1 root root 4 ene 28 16:58 disable-sdmmc-hwcq
-r--r--r-- 1 root root 4 ene 28 16:58 disable-tegra-wdt
-r--r--r-- 1 root root 4 ene 28 16:58 enable-debug-console
-r--r--r-- 1 root root 4 ene 28 16:58 enable-denver-wdt
-r--r--r-- 1 root root 4 ene 28 16:58 enable-pcie-on-uphy-lane4
-r--r--r-- 1 root root 4 ene 28 16:58 enable-sata-on-uphy-lane5
-r--r--r-- 1 root root 4 ene 28 16:58 enable-xusb-on-uphy-lane0 
-r--r--r-- 1 root root 4 ene 28 16:58 enable-xusb-on-uphy-lane1
-r--r--r-- 1 root root 4 ene 28 16:58 enable-xusb-on-uphy-lane2
-r--r--r-- 1 root root 9 ene 28 16:58 name
-r--r--r-- 1 root root 4 ene 28 16:58 no-battery
-r--r--r-- 1 root root 4 ene 28 16:58 normal-flashed

The problem stills when I attach an USB 3.0 Camera it is detected as high-speed.

in the /hardware/nvidia/platform/t18x/quill/kernel-dts/tegra186-quill-p3489-1000-a00-00-base.dts file I have the PCIe configuration as you suggested:

   pcie-controller@10003000 {
		status = "okay";

		pci@1,0 {
            nvidia,num-lanes = <2>;//<4>;
            nvidia,disable-clock-request;
			status = "okay";
			//status = "disabled";
		};
        pci@2,0 {
            nvidia,num-lanes = <1>;//<0>;
			status = "okay";
			//status = "disabled";
        };
        pci@3,0 {
            nvidia,num-lanes = <1>;
			//status = "okay";
			status = "disabled";
		};
		
    };

I am not sure if I have to add in the same file a node for the usb3-2 in the pinctrl@3520000 node like

	usb3-std-A-port2 {
				nvidia,lanes = "usb3-0";
				nvidia,port-cap = <TEGRA_PADCTL_PORT_HOST_ONLY>;
				nvidia,oc-pin = <1>;
			};

but I don know what name should be set to the node.

Thank you.

Hello Wayne,

After the changes that you mention the problem was with the cable, we were using one that was crossing TX and RX making the 3.0 communications fail.

Thank you for the support!