How to configure the MDIO and MDC pins as i2c

[Thirumalesh]

Hi,
I am RGMII interface on jetson agx orin to communicate with ksz9896c switch.
pinmux,gpio configuration and dts file are correct. i verified with clocks coming from Rx and Tx.
From KSZ9896c i am able to get RXCLK and From orin TXCLK.

In ifconfig tool i am able to see eth0 .

But I am facing pinging issue.

I contacted the microchip people they said
please take care of this point, this is an important point. As per the forum link that I shared yesterday Nvidia Soc does not provide TXC timing delay. Please check with your MAC vendor to know if it follows RGMII v1.3 or v2.0 specifications and check if there is a delay provided by the TXC pin or not. if not, then provide a delay in either PCB trace (or) use ingress delay of KSZ9896 TXC through register writing to KSZ9896 switch

so,Can i use MDIO and MDC pins as I2C pins for configuration.

In my hardare MDIO and MDC are connected to (MIIM/i2C/SPI) multiplex pin of KSZ9896c.

[carolyuu]

Hi,

If you are designing a custom base board, then it means some adaptation configurations are needed.
Otherwise, your board may not work fine.

For Orin AGX series, you could refer to below document

Jetson AGX Orin Platform Adaptation and Bring-Up — NVIDIA Jetson Linux...

(please be aware that above link is for rel-36.3/jetpack6.0)

This document includes below configuration

1. pinmux change & GPIO configuration
2. EEPROM change as most custom boards do not have an EEPROM on it.
3. Kernel porting
4. PCIe configuration
5. USB configuration
6. MGBE configuration
7. RGMII configuration

Thanks!

[Thirumalesh]

In document referring to pinmux spreed sheet.In that there is not I2C configuration. that means I2C on MDIO and MDC pin are not possible.

[KevinFFF]

Hi Thirumalesh,

Are you using the devkit or custom board for AGX Orin?
What’s the Jetpack version in use?

It seems you want to port KSZ9896C on Jetson.
Could you share the block diagram of your connections and the full dmesg for further check?

[Thirumalesh]

Nvidia Soc does not provide TXC timing delay. Please check with your MAC vendor to know if it follows RGMII v1.3 or v2.0 specifications and check if there is a delay provided by the TXC pin or not. if not, then provide a delay in either PCB trace (or) use ingress delay of KSZ9896 TXC through register writing to KSZ9896 switch that I mentioned yesterday in the messages, please refer to this knowledge base article for better clarity Microchip Lightning Support

I am using custom board,jetpack 6 version.
In KSZ9896C MDIO/SDI/SDA are multiplexed on pin 97 and MDC/SDL are multiplexed on pin100.

KSZ9896C is stand alone ethernet switch no need of driver for it,
I want to configure one register in KSZ9896C through the I2C.
For I2C communication i want to change the MDIO and MDC to I2C.
In pinmux spreed sheet there is not provision for o change the MDIO and MDC to I2C.

Can you send any reference for me.

ethLog13th.txt (130.2 KB)

[KevinFFF]

I’m checking the your schematic with internal.

@Thirumalesh

For I2C communication i want to change the MDIO and MDC to I2C.
In pinmux spreed sheet there is not provision for o change the MDIO and MDC to I2C.

These 2 pins(D54, 49) can not be used for I2C.
Have you tried to connect your ksz9896c switch on other available I2C bus?

[Thirumalesh]

tried in available I2C bus its working.
i gone through pinmux in TRM document, In theMDIO and MDCC pins cannot use as I2C bus.
@KevinFFF thanks for response.

but I am facing issue with pinging.

in ifconfig eth0 is showing.

TXCLK from orin generating 125MHz and RXCLK from KSZ switch also generating 125MHz.

please find attachment.
eth0_Log17th.txt (13.3 KB)
tegra234-base-overlay.dtsi.txt (19.4 KB)
tegra234-mb1-bct-gpio-p3701-0000-a04.dtsi.txt (4.8 KB)
tegra234-mb1-bct-pinmux-p3701-0000-a04.dtsi.txt (63.6 KB)

I observed flow control is off in look into dmesg.

[KevinFFF]

Please use Figure 8-1 Ethernet Connections in the AGX Orin Design Guide as reference for RGMII interface connectivity and refer to Note 2 below Table 8-3 RGMII Signal Routing Requirements for RGMII-ID is not supported.

[Thirumalesh]

microchip people commented as below.

From device tree file you seem to be configuring RGMII MAC to PHY mode since you are using phy-handle.

Please configure the RGMII in MAC to MAC since you are using KSZ9896 switch. To confirm the MAC to MAC mode, please ensure Device Tree explicitly contains a “fixed-link” sub node under the Nvidia Ethernet MAC node without any PHY references (phy-handle), you could remove the phy-handle line.

I need to follow

For Switch

Prerequisites

1. Ensure that the Switch port is configured for XFI 5G or XFI 10G.
2. Ensure that before Orin boots up, the Switch is powered on an dthat the port is configured.

/* 1:10G, 0:5G / nvidia,uphy-gbe-mode = <1>; / 0:XFI 10G, 1:XFI 5G, 2:USXGMII 10G, 3:USXGMII 5G */ nvidia,phy-iface-mode = <0> nvidia,max-platform-mtu = <16383>;
fixed-link {
speed = <10000>;
full-duplex;
};

Here are the DT entries that are necessary to connect the 10G MAC with the third-party Ethernet switch:

• nvidia,uphy-gbe-mode: 1/0 based on the switch port configuration
• nvidia,phy-iface-mode: 0/1 based on the switch port configuration.
• Add the fixed-link node with speed 10G/5G based on the switch port configuration

[Thirumalesh]

He D54 and k49 wee are not using.

E6 and E7 are using for RGMII interface MDIO and MDC pin.
from orin shall i configure E6 and E7 as I2C pins.

[sgursal]

Try configuring them in pinmux as below snippet. MDIO/MDC signals are push-pull / actively driven and not open drain like I2C signals.