How to connect PCIe?

[LasseRoedtnes]

Hi there!

I’m new to PCI Express so I could use a little assistance on how to connect a PCIe CFExpress in a Gen3x2 configuration to my TX2 custom board.

This is the schematics symbol for the CFExpress card and as you can see there’s two receiver lanes PER0/1 and two transmitter lanes PET0/1 but looking at the TX2 PEX signals it’s not readily apparent to me how I obtain such a configuration? (How do I wire it up)

I understand that CFExpress is PCIe Gen 3 and that TX2 is only Gen 2 will this be a problem or will the CFexpress card just run slower?

I did look at the TX2 design guide, but this table doesn’t make much sense to me to be honest:

On my Carrier Board I would like to have the CFExpress card connected and also 1x USB3 host port so looking at the table above that appears to be Configuration 5 - looking at the following diagram:

I think I can deduce the following, Would this be the correct configuration?

[Trumany]

Hi, please refer to the TX2 Design Guide and devkit carrier schematic for this.

[LasseRoedtnes]

Hi @Trumany

I’ve been look at it for hours and it still doesn’t make total sense to me.

What I’m in doubt about is the lane assignment not so much the electrical signals.

Is it a valid combination to use:

PEX0_CLK/RX/TX in combination with USB-SS1_RX/TX pins so that PEX0 is lane 0 and USB-SS1 is lane 1 on the same PCIe interface leaving USB-SS0 available for USB3 ?

Thanks
Lasse

[Trumany]

Only the configs in lane mapping configurations are supported. Which config (1~6) do you want to use?

[LasseRoedtnes]

Hi Trumany

I need one USB3 port and then the CFExpress card which requires 2 lanes.

Which configuration shall I use (I assume config 5) and if so is my lane assignment correct ?

Yt
Lasse

[Trumany]

It depends on your chose and then use the lanes accordingly. Design Guide has given clear configs and lane mapping.

[LasseRoedtnes]

Hi @Trumany

Sorry but If it was clear, I wouldn’t be asking questions…

Can I use the default 4 lane configuration (Configs 2 CB-Default) in the lane mapping table and then connect only Lane 0 and 1 to my CFexpress card and leave Lanes 2 and 3 unconnected (with RX pins grounded)? Is this a valid usecase for the PCIe interface?

Thanks
Lasse

[Trumany]

Yes, it has been answered in DG as below showing. RX pins can be left unconnected as you can find in chapter 15.0 UNUSED INTERFACE TERMINATIONS in DG.

[LasseRoedtnes]

Thank you it is all clear now.