We just noted that our seL4 test suite proceeds farther without I-cache enabled and the kernel running in EL1 does not hang. With I-cache enabled the lockup is complete and the Lauterbach cannot connect the CCPLEX cores anymore. Naturally it is our desire to have the I-cache enabled.
The seL4 kernel can be run in EL1 with user apps at EL0, or it could be run as a hypervisor in EL2, with user applications at EL1 and EL0. We also ran into very peculiar issue where a RAM page was mapped (meant to be accessible from EL1), data caches were cleaned and TLBs were invalidated. Yet the access to that page resulted in Data Abort, translation fault at level 3. And we dumped the page tables for that TTBRx_ELx setting and the translation should have succeeded. At this point we switched using seL4 at EL1/EL0 to using it at EL2/EL1 and this problem went away, suggesting there could be some stage-2 related MMU settings to be verified (CBOOT runs at EL2 and is supposed to turn MMU off, but we will need to investigate).