How to disable CPU cache?

Robotics & Edge Computing Jetson & Embedded Systems Jetson AGX Xavier
1

Hi,

I’m wondering how could I disable CPU cache L1 and L2 of Xavier?

Thanks.

2

Looks like need write the CPU reg to disable it by ASM language.

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0092b/ch04s04s06.html

3

Hi zorrolee777,

What is the use case that you need caches to be disabled?

Its not straight forward to disabled the caches. But system can be configured to have all write commands go to the memory.

Considering data consistencies:
If CPU is the only entity in your case, than it does not matter if caches are enabled or disabled. CPU will always find similar data in write and read.
If there is any IO device involved, than this can be achieved by coherency. Coherency can be achieved by various modules which kernel already supports them.

The above example is based on only one scenario (data consistency). If you are looking for something else, please help us with your actual use case.

Thanks & Regards,
Sandipan

4

Hello Spatra,

We’re going to do a radiation test on it and we want to disable the cache of it and observe its performance under the radiation.

We have tried to use ASM, and got “illegal instruction (core dumped)”.Here is our code.

#include <stdio.h>
#include <string.h>
#include <linux/kernel.h>
#include <sys/syscall.h>
#include <unistd.h>

void L1_off(void){
	
	__asm__("mrs x1, sctlr_el1;"		// read SCTLR_EL1
                "ldr x1, = 0xefff;"
		"and x11, x11, x1;"		// turn off bit 12 and store into R1 0xefff
                "msr sctlr_el1, x11;");		// restore R1 into SCTLR_EL1

}

void L1_on(void){
	__asm__("mrs x11, sctlr_el1;"
                "ldr x2, = 0x1000;"
		"orr x11, x11, x2;"		// turn on bit 12 
		"msr sctlr_el1, x11;");
}

int main(void){

	L1_off();
	//L1_on();	
	return 0;
}

I’m looking forward to getting some feedback about how to disable the CPU cache of Xavier.

Thanks,
Zorrolee

5

You need to clear SCTLR_EL1.C bit[2] also for data and unified cache.
Illegal instruction coming because register can’t be accessed from Userspace. Also, we can’t disable cache after boot.
ARM32 had macro’s to disable them with config’s CONFIG_CPU_DCACHE_DISABLE & CONFIG_CPU_ICACHE_DISABLE. But this is not present in ARM64.
We are checking if they can be disabled during boot.
By the way, Tegra ARM cache has ECC enabled, so its suited for radiation usecase.

6

Hello sumitg,

Have you figured out whether the CPU cache could be disabled during boot?

Thanks