Is PCIe TX/RX are reversible?

Autonomous Machines Jetson & Embedded Systems Jetson Xavier NX
1

Hello,

I have designed my own carrier board for Xavier NX to be capable to work with M.2 PCIe slot. At time of design there was no reference schematics yet, so I designed the PCIe based on the DG-09693-001_v1.2 DG, application notes, and standards dealing with PCIe.

Now, it seems, all data 4 lanes in my design are reversed, compared to the Jeston Xavier NX evaluation board.
Here is a summery table (see attached pcie cconnection table.txt)that describes connection of what has been done, compared to the NVDIA Xavier NX platform.

                    **SODIMM**                                 **My board M.2 Key M**      **Xavier NX P3509_A01**

PCIE0_TX0P/0N (pin 136/134 via serial cap) => REPp0/n0 (Pin 43/41) PETp0/n0 (Pin 49/47)
PCIE0_TX1P/1N (pin 142/141 via serial cap) => REPp1/n1 (Pin 31/29) PETp1/n1 (Pin 37/35)
PCIE0_TX2P/2N (pin 150/148 via serial cap) => REPp2/n2 (Pin 19/17) PETp2/n2 (Pin 25/23)
PCIE0_TX3P/3N (pin 156/154 via serial cap) => REPp3/n3 (Pin 7/5) PETp3/n3 (Pin 13/11)

PCIE0_RX0P/0N (pin 133/131) => PETp0/n0 (Pin 49/47) REPp0/n0 (Pin 43/41)
PCIE0_RX1P/1N (pin 139/137) => PETp1/n1 (Pin 37/35) REPp1/n1 (Pin 31/29)
PCIE0_RX2P/2N (pin 151/149) => PETp2/n2 (Pin 25/23) REPp2/n2 (Pin 19/17)
PCIE0_RX23/3N (pin 157/155) => PETp3/n3 (Pin 13/11) REPp3/n3 (Pin 7/5)

Searching Nvidia forum I found:

** Jetson NX M.2 Key M slot supports both lane reversal and polarity reversal. Hardware takes care of it, no need for extra software programming. However there is one limitation, lane reversal fails if we want to get the link up in x1. If you are using complete x4, then lane reversal works without any issue.**

Unfortunately in my case the lspci shows no result.
I would appreciate your support and ideas how to fix it and what to check.

Attached is “dmesg | grep pci” output.dmesg_pci.txt (3.2 KB)

I’m using Lexar NM700 M.2 2280 Gen3X4 NVMe SSD card.

Thanks,
Just realized that the table was not copied on the correct order. I’m reattaching it in a txt file.
Andreypcie cconnection table.txt (884 Bytes)

3

Lane reversal means lanes-0,1,2,3 going to lanes-3,2,1,0 and polarity reversal means swapping Tx+ to Tx- and/or Rx+ to Rx-
If the above is what is present in the design, it should work.
Typically, Tegra’s Tx lanes go to endpoint’s Rx lanes and endpoint’s Tx lanes come to Tegra’s Rx lanes. But, in your design, I think we have Tx lanes of Tegra going to Tx lanes of the EP right? If so, it doesn’t work.

4

Hi vidyas,

Thanks for your replay. The status quo is understood. I would like just to point to the specification of PCIe and share the page

SSD Socket Key M
SSD Socket Key M621×898 104 KB

dealing with M.2 socket for SSD devices, where Tp is probably stands for transmit(of EP I guess), while the Rn stands for receive(of EP), while in the reference schematics of Xavier NX P3509_A01 it is opposite.

Thanks and Regards,

5

Re: But, in your design, I think we have Tx lanes of Tegra going to Tx lanes of the EP right? Yes, it seems so.

6

Ok… in that case… it is expected that the link doesn’t come up.