I’m using the Jetson AGX as a root port and a Xilinx dev board as PCIe endpoint. PCIe connection is well established and data correctly exchanged. I configured a user IRQ sent by the endpoint over PCIe and I’m using MSI-X interrupts. By default, IRQ affinity is setup to the CPU0 core of the Jetso…

The affinity of a single MSI interrupt can’t be changed, but the all the interrupts can be changed by changing the CPU affinity of tegra-pcie-msi interrupt. There are 2-4 entries of it on AGX Xavier, so you may have to find which one affects it. It would have been great if each MSI interrupt’s affi…

Jetson AGX Xavier IRQ over PCIe CPU affinity can't be changed

Robotics & Edge Computing Jetson & Embedded Systems Jetson AGX Xavier

nicolas.bon December 7, 2020, 1:26pm 10

Thanks, I tried isolating one cpu core to dedicate it the handle my IRQ ISR but I’m still experiencing some high transfer values.

I’ve opened another discussion in the forum to talk about this (PCIe IRQ latency unbounded value).

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Jetson AGX Xavier IRQ over PCIe CPU affinity can't be changed

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