Hi! Sir
https://devtalk.nvidia.com/default/topic/962847/?comment=4995007 #13
drivers/platform/tegra/tegra21_clocks.c
#define USE_PLLE_SS 0
#if USE_PLLE_SS
val = clk_readl(PLLE_SS_CTRL);
val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);
val &= ~PLLE_SS_COEFFICIENTS_MASK;
val |= PLLE_SS_COEFFICIENTS_VAL;
clk_writel(val, PLLE_SS_CTRL);
val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);
pll_writel_delay(val, PLLE_SS_CTRL);
val &= ~PLLE_SS_CNTL_INTERP_RESET;
pll_writel_delay(val, PLLE_SS_CTRL);
#endif
include/linux/platform/tegra/clock.h
#ifdef CONFIG_ARCH_TEGRA_2x_SOC
#define USE_PLL_LOCK_BITS 0 /* Never use lock bits on Tegra2 /
#else
#define USE_PLL_LOCK_BITS 1 / Use lock bits for PLL stabiliation /
#define USE_PLLE_SS 0 / Use spread spectrum coefficients for PLLE /
#define PLL_PRE_LOCK_DELAY 2 / Delay 1st lock bit read after pll enabled /
#ifdef CONFIG_ARCH_TEGRA_3x_SOC
#define PLL_POST_LOCK_DELAY 50 / Safety delay after lock is detected /
#else
#define USE_PLLE_SWCTL 0 / Use s/w controls for PLLE /
#define PLL_POST_LOCK_DELAY 10 / Safety delay after lock is detected */
#endif
#endif
We has tried Without https://devtalk.nvidia.com/default/topic/962847/?comment=4995007 #13 and
With https://devtalk.nvidia.com/default/topic/962847/?comment=4995007 #13
The measured waveforms there is no difference between above two waveforms when disable SSC (Spread Spectrum Clocking) PEX_CLK0_P & PEX_CLK0_N on Jetson TX1 Developer Kit.