L4T PCIe BAR Mapping Addressing Space

Hi.

Would you please tell me the maximum PCIe BAR mapping address space size of Jetson TX2 with Linux4Tegra?
I understand that the Parker SoC supports the BAR 64-bit addressing from the Parker TRM, but I’d like to know if Linux4Tegra has any restrictions for that.
Thank you.

Yes Parker SoC does support 64-bit BARs and total amount of space available to map end points BARs is 640MB for prefetchable BARs and 127 MB for non-prefetchable BARs

vidyas,

Thank you very much for your reply.
So, can Parker Soc map endpoints to anywhere in 64-bit PCIe address space?
I understand that the accessing window of Parker side is restricted to PCIE1, PCIE2 and Reclaimable PCIe.

Best regards.

Nope. It can map only to PCIE1, PCIE2 and reclaimable PCIe (you understanding is correct)

Nope. It can map only to PCIE1, PCIE2 and reclaimable PCIe (you understanding is correct)

vidyas,

I understand that PCIE1, PCIE2 and reclaimable PCIe are on the Parker SoC side address space.
But I’d like to know if Paker SoC can map endpoints to anywhere in the 64-bit PCIe address space with the PCIe 64-bit addressing capability.

Thanks.

I’m not sure if I understood your question properly.
Since PCIe owns the region (0x4000_0000 ~ 0x7000_0000) which is in 32-bit address space and which it uses for mapping end point devices’s BARs, it can not use any of 64-bit address space (i.e. > 0xFFFF_FFFF) for this purpose.

vidyas,

Thank you very much for your reply.
According to the Parker SoC TRM, the PCIe module supports 64-bit address.
I assume that Parker can map a region in PCIe virtual 64-bit address space to the physical region (0x4000_0000 ~ 0x7000_0000).
I’d like to know if we can use whole the virtual 64-bit address space of Parker SoC.

Best regards.

the PCIe module supports 64-bit address
I think the above statement means that PCIe IP can access 64-bit addresses coming in from endpoint devices for memory read/write accesses.

Can you give more info about “PCIe virtual 64-bit address space”. what are you referring to by this?

I assume that the following address translations exist in a PCIe system.

Root Complex Physical Address<–Translation–>PCIe Virtual Address<–Translation–> Endpoint Device Physical Address

My question is if I can assign the BAR of Endpoint side to an address over 32-bit space.
e.g. Endpoint BAR address is located at 0x3_0000_0000 in PCIe virtual address, then Parker SoC accesses the BAR through own local 0x4000_0000.

Any specific reason in calling it as ‘PCIe Virtual Address’ instead of just ‘Virtual Address’ as ultimately it is CPU that is going to access this virtual address?
Also, this could be any address depending on what ioremap() returns or the virtual address that is being exclusively mapped to point to 0x4000_0000 physical address.

The PCIe virtual address is not Linux virtual address.
The PCIe specification defines PCIe own (32-bit / 64-bit) address space which is shared with Root Complex and Endpoints.
Maybe I need to reconsider my question, then I’ll come back to this thread. Thank you very much for your support.

Yes Parker SoC does support 64-bit BARs and total amount of space available to map end points BARs is 640MB for prefetchable BARs and 127 MB for non-prefetchable BARs

I’m not sure if I understood your question properly.
Since PCIe owns the region (0x4000_0000 ~ 0x7000_0000) which is in 32-bit address space and which it uses for mapping end point devices’s BARs, it can not use any of 64-bit address space (i.e. > 0xFFFF_FFFF) for this purpose.

Hello vidyas,
I am not able to verify these information on the datasheets. Would you please point to the related datasheets?

thank you,
Fatih.