Yes Parker SoC does support 64-bit BARs and total amount of space available to map end points BARs is 640MB for prefetchable BARs and 127 MB for non-prefetchable BARs
I’m not sure if I understood your question properly.
Since PCIe owns the region (0x4000_0000 ~ 0x7000_0000) which is in 32-bit address space and which it uses for mapping end point devices’s BARs, it can not use any of 64-bit address space (i.e. > 0xFFFF_FFFF) for this purpose.
I am not able to verify these information on the datasheets. Would you please point to the related datasheets?