Six months ago, I came here and said that I believed the industry was moving in the wrong direction.
More transistors.
More power.
More memory traffic.
More brute force.
But the fundamental computational model remains largely the same.
I was critical about that direction then.
My opinion has not changed.
The difference is that six months ago I was arguing.
Today I am bringing hardware and code.
During these six months I developed:
- two generations/branches of experimental computing cores;
- R-Core as a persistent-state computational architecture;
- V-PACK as a separate deterministic state representation and reconstruction technology;
- multiple later architectural generations;
- and the initial computational foundation of an AGI architecture built around this work.
My seventh-generation architecture has already progressed into patent filing.
But I am not publishing Gen7 here.
Today I am giving you R-Core Generation 1.
The old one.
The weaker one.
The one that came first.
And I am doing that deliberately.
If the underlying idea is wrong, Generation 1 should already contain enough information to expose the failure.
If the underlying idea is right, then this first generation should also be enough to understand why I continued developing it.
What is R-Core Gen1?
R-Core Gen1 is a real FPGA-oriented computational core built around a persistent internal state.
The reference architecture contains:
- 343 logical processing nodes;
- a 7 × 7 × 7 topology;
- persistent internal state;
- Q2.14 fixed-point representation;
- six local face-neighbour connections;
- addressed external state injection;
- deterministic global-state evolution;
- double state banks;
- atomic state-bank switching after a completed global update.
343 nodes are not the architectural limit.
7 × 7 × 7 is not the architectural limit.
They are simply the first physical implementation.
The original target was a Tang Primer 20K FPGA.
That FPGA is small.
Its logic resources are limited.
Its memory resources are limited.
Its clock performance is modest compared with modern GPU hardware.
But that was enough for one important purpose:
to move the architecture from an idea into real RTL and a physically implementable machine.
Why I am publishing Generation 1
I could publish another long theoretical post.
I could describe where Generation 7 has already moved.
I could describe the architecture I am now using as the foundation for my AGI work.
I am not doing that.
Instead, I am putting the old core on the table.
The main RTL core is attached to this post.
The validation report is attached.
The Python golden/reference implementation is attached.
The README is attached.
The RTL can be inspected line by line.
The deterministic regression can be reproduced.
The architecture can be criticized.
It can be profiled.
It can be mapped onto CUDA.
It can be broken.
That is much more useful than another argument.
This is not a CUDA benchmark claim
I am not publishing a statement such as:
“R-Core is X times faster than an NVIDIA GPU.”
There is no honest basis for such a statement yet.
R-Core does not naturally behave like a conventional linear sequence of isolated arithmetic operations.
It is a persistent-state architecture.
The state remains inside the computational structure and evolves.
The nodes influence the evolution of other state.
Therefore comparing a single multiplication, FLOPS number, or clock frequency would not answer the important question.
The real test is scaling the architecture itself:
- number of persistent states;
- update rate;
- connectivity;
- synchronization;
- memory traffic;
- propagation latency;
- state locality;
- energy per useful state transition;
- and eventually learning/state-reconstruction workloads.
That is the benchmark I am interested in.
Why post this on an NVIDIA forum?
Because NVIDIA engineers understand parallel computation.
And because NVIDIA itself was once the company pushing in a direction that many established players did not initially consider the center of computing.
I am now pushing against another assumption:
that the current CPU/GPU execution model is necessarily the final computational substrate for machine intelligence.
I do not believe it is.
I said that six months ago.
I still believe it today.
The difference is that I now have considerably more than an argument.
AGI
Yes, this work is connected directly to AGI.
I have already begun building an AGI architecture around the later R-Core generations.
Not an API wrapper.
Not another chatbot interface.
Not simply another transformer implementation with a different name.
I am working from the computational substrate upward:
persistent state,
memory,
state evolution,
connectivity,
learning,
world-state representation,
and mechanisms through which the system can accumulate and transform internal structure over time.
R-Core Gen1 is an ancestor of that work.
It is not the current architecture.
It is the version I am willing to put in public today so that engineers can inspect something real.
Six months
Six months ago, I came here with a position.
Today I return with:
R-Core hardware architecture.
A working Generation-1 RTL implementation.
Later generations already developed.
V-PACK.
Patent-filed architectural work.
And the first foundation of an AGI system.
So I will say one thing very clearly.
If this direction is ignored now, then in another six months the question may no longer be whether it deserves attention.
The question may be how far it moved while people were still deciding whether it was worth looking at.
I am not asking NVIDIA for permission.
I am not asking anyone to approve the architecture.
I am not asking anyone to believe me.
I am giving you the first-generation core.
Open it.
Read it.
Test it.
Break it if you can.
I will continue building either way.
Attached
- R-Core Gen1 README
- R-Core Gen1 main RTL core
- R-Core Gen1 validation report
- R-Core Gen1 Python golden/reference implementation
The source files are attached as “.txt” only for forum compatibility. After downloading, they can be renamed back to their original “.sv” / “.py” extensions.
This public package contains Generation 1 only.
Generation 7 and the current AGI implementation are not included.
R-CORE_GEN1_NVIDIA_PUBLIC.zip (266.6 KB)
09_R_CORE_GEN1_VALIDATION-2.txt (4.7 KB)
01_R_CORE_GEN1_LATTICE_CORE__RENAME_TO_SV-1.txt (11.0 KB)