ODMDATA Configuration For Xavier NX

We designed Carried Board for Xavier NX, flashed BSP. And the OS boot successfully.
But the mini-PCIe device that connected to PCIE1 by pcie slot can not be recognized.
After reading the document “Tegra_Linux_Driver_Package_AGX_Xavier_Adaptation_Guide.pdf”,
I think maybe there are some mistakes on ODMDATA about pcie configuration.

Below is ODMDATA value from p3668.conf.common file.

And I checked the device tree values used at runtime.
ls /proc/device-tree/chosen/plugin-manager/odm-data/


What means are these files ?
How to modify the ODMDATA to enable PCIE1?

dmesg info:dmesg.log (64.6 KB)


Tegra_Linux_Driver_Package_AGX_Xavier_Adaptation_Guide is only for Xavier but not NX. The new document for NX is not yet published.

Why do you need to modify ODMATA? Are you using pin PCIE1_RX/TX, PCIE1_RST… here to replace the M.2 key E slot on devkit? If so, then you don’t need to update ODMDATA because we already enabled it.

Hi, WayneWWW

On our carried board,we use a PCIe switch to expand the PCIE1 interface into 3 pcie x 1 (a GBE, a M.2 key E , an mPCIe slot). Now none of these three devices are recognized.


This sounds not related to uphy or ODMDATA. Are you able to see anything in lspci?

I can see nothing about PCIE1 in lspci.
I can see PCIEx4 ‘s infomation in lspci .

Xavier NX devkit supports C4 and C5 controllers, so only these controllers are enabled in DT. Any changes in base board needs update in device tree. Apply attached patch which enable PCIE1 and boot the device with it. Also, based on your base board design we may need to make further changes in device tree, provide complete PCIe configuration details of your base board.

Note: Remove .txt extension from patch file and then apply.

0001-Enable-PCIe-C1-for-devtalk-forum-bug.patch.txt (1.0 KB)


After I patched [0001-Enable-PCIe-C1-for-devtalk-forum-bug.patch] ,
from dmesg I can find some information like [pci_bus 0001 …], but I can’t see anything in lspci.
and devices connected to PCIE1 also are not recognized.

dmesg: dmesg_2.log (66.0 KB)
PCIE1 Sch:

I reviewed Xavier NX module schematics and found out that PCIE1 is controller C4, so no need for the patch attached in previous comment. Release build should work fine for this configuration. PCIE1 is verified on the devkit via M.2 KeyE connector, so I don’t think any SW changes are required. Apply the attach patch to disable PCIe power down, this will help us do some experiments.

  1. Please verify PCIe signals in the scope and check if signals are as expected.
  • PCIE1_RST: Should be deasserted when PCIe driver is starting LTSSM
  • PCIE1_CLK_P & PCIE1_CLK_N 100MHz differential clock.
    Probing data lines are difficult, so I wouldn’t recommend it.
  1. After booting capture “sudo /home/ubuntu/reg_dump -a 0x141600d0 -s 0x4” 5 times with a delay for ~1 second.
  2. If you have PCIe protocol analyzer, please capture the traces, we can verify LTSSM sequence.

Manikanta0001-DNI-Xavier-NX-Disable-power-down-for-C4.patch.txt (921 Bytes)

1 Like


I disabled PCIe power down of CPIE1, In lspci, infomation of controller C4 is shown as below.
$ lspci
0004:00:00.0 PCI bridge: NVIDIA Corporation Device 1ad1 (rev a1)

But the device is still not detected on our base board.
And I can’t find command “sudo /home/ubuntu/reg_dump -a 0x141600d0 -s 0x4”.
Our hardware engineer is now checking the PCIe signals .
Thanks a lot!


We checked the signals , PCIE1_RST and 100MHZ clock signals are normal output.
But the PCIe Switch connected to PCIE1 and the pcie devices connected to PCIe Switch are not recognized.
I attach the pcie1’s schematics , If any HW or SW needs to be changed, could you give me some indications ?
remove the suffix “.doc” PCIe1+(Switch).pdf.doc (69.1 KB)


I double checked the PCIe signal connections, they are fine. I checked PI7C9X2G608GP specifications, it says that there is “Integrated 100MHz Clock buffer for each downstream port”. Does that mean PI7C9X2G608GP operates with SRIS(Separate Reference Clock with Independent Source)? Tegra PCIe has spread enabled, so it won’t support endpoints with SRIS.

Few more thoughts,

  1. You can try limiting link speed to Gen2, if at all there are any issue with setting TLS to Gen3.
    Add nvidia,max-speed = <2>; in pcie device tree node to restrict link speed to Gen2.
  2. If you have a CEM slot compatible card with PI7C9X2G608GP, try it on Jetson AGX. PCIe IP is same in Jetson AGX & NX, this will rule out any compatible issues with Tegra PCIe. If you see link up issue here, you need to capture PCIe protocol traces to root cause the issue.



Thank you for your great help and patience.
We changed the device tree node releted to PCIE1 as your suggestion that to add nvidia,max-speed = <2>; , but it does not work, nothing seems to be changed.

We suspect that the problem is on the PCIE switch PI7C9X2G608GP.

This PI7C9X2G608GP has been used with TX2 and AGX , is it different between NX and AGX ?



There is no difference between NX & AGX wrt HW.
In SW odmdata is difference between NX & AGX, it as per the module design.
Are you using exactly same carrier board on NX & AGX?