Hello ShaneCCC,
We are deriving mipi clocks in the same way from this post - VI cannot recv any data form tc358743 - #13 by ShaneCCC
For a 720p60 UYVU (16bits for color) :
Calculation:
Total pixels per frame: 1650 × 750 = 1,237,500 pixels
Bits per pixel for UYVY: 16 bits
1,237,500 × 16 = 19,800,000 bits per frame
Bits per second: 19,800,000 × 60 fps = 1,188,000,000 bits/second
Assuming 2 lanes:
1,188,000,000 ÷ 2 = 594,000,000 bits per lane
CSI clock frequency calculation:
1,188,000,000 ÷ 4 = 297 MHz (remains the same)
So for two-lane configuration:
bits_per_lane: ~594 Mbps
csi_clk_freq: 297 MHz
And that is what I’m getting:
[10122.426932] t194-nvcsi 13e00000.host1x:nvcsi@15a00000: X- NEW2 mipi_clock_rate is : 297000
I noticed it used to be calculated in csi5_fops.c like this:
cil_config.mipi_clock_rate = tegra_chan->subdev[index]->bps_per_lane / 2000;
But bps_per_lane is not defined in the csi5_fops.c - so I have currently hardcoded the value.
Is 297000 correct? And would that be the same for 4 land 1080p60 video?
For PHY mode, I see this :
[10122.426920] t194-nvcsi 13e00000.host1x:nvcsi@15a00000: X-- brick_config.phy_mode : 0
[10122.426924] t194-nvcsi 13e00000.host1x:nvcsi@15a00000: X-- brick_config.lane_polarity[index] : 0
[10122.426927] t194-nvcsi 13e00000.host1x:nvcsi@15a00000: X-- csi5_stream_set_config : before s_data
[10122.426930] t194-nvcsi 13e00000.host1x:nvcsi@15a00000: X-- using hardcode 5940
[10122.426934] t194-nvcsi 13e00000.host1x:nvcsi@15a00000: X-- sizeof(msg) is : 280
[10122.426936] t194-nvcsi 13e00000.host1x:nvcsi@15a00000: X-- valid ports is : 1
[10122.426938] t194-nvcsi 13e00000.host1x:nvcsi@15a00000: X-- vi port is : 0
Does that look correct?
Thank you.