Ov01f10-max96701-max96712 orin capture error

[fengrongsu]

orin_dts.dts (13.6 KB)
Hi,
I use ov01f10-max96701-max96712 and orin to bring up the cameras,I tried many ways to get the image but failed, Please help.
Several parameters i have tried,please help me to check.
1.pix_clk_hz
The sensor output size is 1280x960@25fps ,so pix_clk_hz is 30720000, is that right?
2.serdes_pix_clk_hz
The mipi output pll frequency of max96712 is configed by reg 0x415

If I want to avoid skew calibration(> 1.5Gbps)，the data rate of one lane must be less than 375Mbs(1.5G/4) which means the DPLL frequency is less than 375Mhz. Is that right?
So set the DPLL frequency 300MHz while the data rate is 1.2Gbps，then serdes_pix_clk_hz = 1.2Gbps x 4 /16 = 300M.
The trace log is:

     kworker/2:1-112     [002] ....    95.325119: rtcpu_nvcsi_intr: tstamp:3644909812 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x00000004
     kworker/2:1-112     [002] ....    95.325119: rtcpu_nvcsi_intr: tstamp:3644910856 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x00000004
     kworker/2:1-112     [002] ....    95.325119: rtcpu_nvcsi_intr: tstamp:3644911900 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x00000004

Besides I also tried to disable the config para serdes_pix_clk_hz,since in other posts which may be helpful when it is yuv sensor.
Here is the trace log with no serdes_pix_clk_hz.

     kworker/1:0-20      [001] ....   287.055503: rtcpu_vinotify_event: tstamp:9638735693 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:308432242144 data:0x0000000031000001
     kworker/1:0-20      [001] ....   287.055504: rtcpu_vinotify_event: tstamp:9638735846 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:308432282592 data:0x719d550010000000
     kworker/1:0-20      [001] ....   287.055504: rtcpu_vinotify_event: tstamp:9638735977 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:308432289120 data:0x0000000031000002

3.mclk_khz
Is mclk_khz the crystal oscillator frequency of max96712?

MIPI data and clock signal can be observed on oscilloscope,the config of serdes and sensor should be correct.I guess it’s the time parameter matching between orin and max96712.

Clock config is also completed.

echo 1 > /sys/kernel/debug/bpmp/debug/clk/vi/mrq_rate_locked
echo 1 > /sys/kernel/debug/bpmp/debug/clk/isp/mrq_rate_locked
echo 1 > /sys/kernel/debug/bpmp/debug/clk/nvcsi/mrq_rate_locked
echo 1 > /sys/kernel/debug/bpmp/debug/clk/emc/mrq_rate_locked
cat /sys/kernel/debug/bpmp/debug/clk/vi/max_rate |tee /sys/kernel/debug/bpmp/debug/clk/vi/rate
cat /sys/kernel/debug/bpmp/debug/clk/isp/max_rate | tee  /sys/kernel/debug/bpmp/debug/clk/isp/rate
cat /sys/kernel/debug/bpmp/debug/clk/nvcsi/max_rate | tee /sys/kernel/debug/bpmp/debug/clk/nvcsi/rate
cat /sys/kernel/debug/bpmp/debug/clk/emc/max_rate | tee /sys/kernel/debug/bpmp/debug/clk/emc/rate

Any advice?I have no idea to have a try next step.

[MarkusHoHo]

Hi @fengrongsu, welcome back in our forums.

May I ask which Orin model you are using? Then i can correctly transfer your post to the experts in the correct Category.

Thanks!

[fengrongsu]

Hi @MarkusHoHo
NVIDIA Orin NX,
Thanks!

[fengrongsu]

@MarkusHoHo any advice?
Help~

[MarkusHoHo]

I am sorry, but this is outside my area of expertise.

The Jetson team will try to reply, but please be patient.

Thanks!

[fengrongsu]

I also try to enable deskew intial calibration by setting reg 0x903 0x943 0x983 0x9c3 bit7 to 1 of max96712.
Then I can increase the data rate.
Changing the DPLL freq from 400MHz to 2.5GHz which means the data rate is between 400bps/lane and 2.5Gbps/lane (total 4 lane)does not make any difference.

Any thing else I can have a try?

[ShaneCCC]

The error tell SOT(Start Of Transfer) error, that could be the settle time don’t match MIPI spec.

     kworker/2:1-112     [002] ....    95.325119: rtcpu_nvcsi_intr: tstamp:3644909812 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x00000004

[fengrongsu]

Hi,Thanks for your reply.
I tried to config some time parameter in SOT,Here is the new trace log

# tracer: nop
#
# entries-in-buffer/entries-written: 21/21   #P:4
#
#                                _-----=> irqs-off
#                               / _----=> need-resched
#                              | / _---=> hardirq/softirq
#                              || / _--=> preempt-depth
#                              ||| /     delay
#           TASK-PID     CPU#  ||||   TIMESTAMP  FUNCTION
#              | |         |   ||||      |         |
     kworker/2:0-25      [002] ....   303.384372: rtcpu_string: tstamp:10174070623 id:0x04010000 str:"VM0 deactivating."
        v4l2-ctl-2558    [001] ....   319.160596: tegra_channel_open: vi-output, ox01f10 10-0011
        v4l2-ctl-2558    [001] ....   319.163658: tegra_channel_set_power: ox01f10 10-0011 : 0x1
        v4l2-ctl-2558    [001] ....   319.163665: camera_common_s_power: status : 0x1
        v4l2-ctl-2558    [001] ....   319.185724: tegra_channel_set_power: 13e40000.host1x:nvcsi@15a00000- : 0x1
        v4l2-ctl-2558    [001] ....   319.185727: csi_s_power: enable : 0x1
        v4l2-ctl-2558    [001] ....   319.186653: tegra_channel_capture_setup: vnc_id 0 W 1280 H 960 fmt 10
        v4l2-ctl-2558    [002] ....   319.192905: tegra_channel_set_stream: enable : 0x1
        v4l2-ctl-2558    [002] ....   319.195190: tegra_channel_set_stream: 13e40000.host1x:nvcsi@15a00000- : 0x1
        v4l2-ctl-2558    [002] ....   319.195192: csi_s_stream: enable : 0x1
        v4l2-ctl-2558    [002] ....   319.195500: tegra_channel_set_stream: ox01f10 10-0011 : 0x1
     kworker/2:2-114     [002] ....   319.244151: rtcpu_string: tstamp:10667965164 id:0x04010000 str:"VM0 activating."
     kworker/2:2-114     [002] ....   319.244153: rtcpu_vinotify_event: tstamp:10668416655 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:341378848192 data:0x719d580010000000
     kworker/2:2-114     [002] ....   319.244153: rtcpu_vinotify_event: tstamp:10668416794 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:341378855072 data:0x0000000031000001
     kworker/2:2-114     [002] ....   319.244154: rtcpu_vinotify_event: tstamp:10668416950 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:341378900384 data:0x719d550010000000
     kworker/2:2-114     [002] ....   319.244154: rtcpu_vinotify_event: tstamp:10668417094 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:341378906944 data:0x0000000031000002
 vi-output, ox01-2560    [000] ....   321.840870: tegra_channel_capture_setup: vnc_id 0 W 1280 H 960 fmt 10
     kworker/2:2-114     [002] ....   321.876140: rtcpu_vinotify_event: tstamp:10750899464 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:344026977632 data:0x719d580010000000
     kworker/2:2-114     [002] ....   321.876141: rtcpu_vinotify_event: tstamp:10750899603 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:344026984096 data:0x0000000031000001
     kworker/2:2-114     [002] ....   321.876142: rtcpu_vinotify_event: tstamp:10750899758 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:344027024448 data:0x719d550010000000
     kworker/2:2-114     [002] ....   321.876142: rtcpu_vinotify_event: tstamp:10750899892 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:344027031008 data:0x0000000031000002

what should i do next?

[fengrongsu]

In other post such as

ERROR: NULL VI channel received, VIFALC_TDSTATE. How can I deal with it?

Hi, I’m enabling a custom sensor which works on AGX Xavier. I’m trying to modify device tree and driver. But I got the errors. dmesg log [ 31.197978] tegra-camrtc-capture-vi tegra-capture-vi: uncorr_err: request timed out after 2500 ms [ 31.198238] tegra-camrtc-capture-vi tegra-capture-vi: err_rec: attempting to reset the capture channel [ 31.199019] (NULL device *): vi_capture_control_message: NULL VI channel received [ 31.199215] t194-nvcsi 13e40000.host1x:nvcsi@15a00000: csi5_stream_clo…

It is about data rate,so I tried to set the data rate both above and below 1.5Gbps.
When the data rate is above,deskew calibration was also enabled.
The log is the same.

[ShaneCCC]

This log tell didn’t receive any validate data from MIPI bus.

Thanks

[fengrongsu]

what should i do next step to fix this problem?

[ShaneCCC]

Please make sure the MIPI signal according to the MIPI spec.

Thanks

[fengrongsu]

I found there is a camera fw released by NV for Orin in other posts

Camera failed with log:VIFALC_TDSTATE on Jetpack5.0.2

Hi, I use a camera that outputs grey to access the jetson system, and it works fine in nano, xavier, and other platforms. But it does not work correctly in orin platform. Here is the log: kworker/3:3-520 [003] .... 922.826162: rtcpu_vinotify_event: tstamp:29561718191 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:945965440160 data:0x379e300010000000 kworker/3:3-520 [003] .... 922.826163: rtcpu_vinotify_event: tstamp:29561718466 cch:0 vi:1 tag:VIFALC_TDSTATE …

Can you share a Latest version of camera fw?

[ShaneCCC]

I don’t think that cold help on it.
Below is the link for it.

Request debug RTCPU image for JP5.1.1

When debugging a MIPI camera for Orin NX, I encountered an issue. It seems that the rtcpu on Orin NX has entered a pseudo-deadlock state, and only a power cycle can restore the Jetson board. Could you provide a debug version of rtcpu and the flashing method? I would like to examine the rtcpu logs to assist in resolving the problem.

[kipade]

Hello ShaneCCC, and is there a way to turn off the skew calibration for orin nx? Since the Xaiver SoC can accept data streams from GSML2 camera with data rate more than 1.5Gbps.

[ShaneCCC]

Sorry to tell unable to turn it off.
Please have sensor send deskew signals if output data rate > 1.5G

Thanks

[fengrongsu]

I can get camera image on xaiver but when the same configs apply to orin it failed.
First,Enable DPHY Deskew Initial Calibration

The kernel log:

   85.660269] [RCE] NVCSILP clock rate = 408000000 Hz.
[   85.660272] [RCE] tegra_nvcsi_stream_set_config(vm0, stream=0, csi=0)
[   85.660273] [RCE] MIPI clock = 750000 kHz, tHS-SETTLE = 0, tCLK-SETTLE = 0
[   85.660274] [RCE] ===== NVCSI Stream Configuration =====
[   85.660276] [RCE] stream_id: PP 0, csi_port: PORT A
[   85.660277] [RCE] Brick: PHY 0, Mode: D-PHY
[   85.660278] [RCE] Partition: CIL A, LP bypass: Enabled, Lanes: 4
[   85.660279] [RCE] Clock information:
[   85.660281] [RCE] MIPI clock rate: 750.00 MHz
[   85.660282] [RCE] T_HS settle: 0, T_CLK settle: 0
[   85.660283] [RCE] ======================================
[   85.660284] [RCE] tegra_nvcsi_stream_open(vm0, stream=0, csi=0)
[   85.660286] [RCE] nvcsi_calc_ths_settle ths_settle 53
[   85.660287] [RCE] nvcsi_calc_ths_settle ths_settle 53
[   85.660288] [RCE] nvcsi_calc_ths_settle ths_settle 53
[   85.660290] [RCE] nvcsi_calc_tclk_settle tclk_settle 75
[   85.760477] ox01f10 10-0011: ox01f10_start_streaming ++
[   85.760487] ox01f10 10-0011: ox01f10_write_table: channel 0, 
[   85.760494] ox01f10 10-0011: ox01f10_write_table: write reg source :0x52 addr:0x40b val:0x42
[   85.772266] [RCE] ISR PHY 0 CIL_A 0x10000000
[   86.808474] ox01f10 10-0011: ox01f10_write_table: write reg source :0x52 addr:0x8a0 val:0x84
[   86.832256] ox01f10 10-0011: ox01f10_start_streaming OX01F10_MODE_START_STREAM 0 ++
[   87.324837] mt7601u 1-3.3:1.0: Error: TSSI upper saturation
[   88.312279] tegra-camrtc-capture-vi tegra-capture-vi: uncorr_err: request timed out after 2500 ms
[   88.321424] tegra-camrtc-capture-vi tegra-capture-vi: err_rec: attempting to reset the capture channel
[   88.332072] (NULL device *): vi_capture_control_message: NULL VI channel received
[   88.339793] t194-nvcsi 13e40000.host1x:nvcsi@15a00000: csi5_stream_close: Error in closing stream_id=0, csi_port=0
[   88.350469] (NULL device *): vi_capture_control_message: NULL VI channel received
[   88.358204] t194-nvcsi 13e40000.host1x:nvcsi@15a00000: csi5_stream_open: VI channel not found for stream- 0 vc- 0
[   88.368976] tegra-camrtc-capture-vi tegra-capture-vi: err_rec: successfully reset the capture channel

So I reduce the deskew width.
When the deskew width reduce to 4x32k UI, the phy ISR disappear.

  57.763493] [RCE] NVCSILP clock rate = 408000000 Hz.
[   57.763498] [RCE] tegra_nvcsi_stream_set_config(vm0, stream=0, csi=0)
[   57.763499] [RCE] MIPI clock = 750000 kHz, tHS-SETTLE = 0, tCLK-SETTLE = 0
[   57.763501] [RCE] ===== NVCSI Stream Configuration =====
[   57.763503] [RCE] stream_id: PP 0, csi_port: PORT A
[   57.763504] [RCE] Brick: PHY 0, Mode: D-PHY
[   57.763506] [RCE] Partition: CIL A, LP bypass: Enabled, Lanes: 4
[   57.763507] [RCE] Clock information:
[   57.763509] [RCE] MIPI clock rate: 750.00 MHz
[   57.763510] [RCE] T_HS settle: 0, T_CLK settle: 0
[   57.763512] [RCE] ======================================
[   57.763513] [RCE] tegra_nvcsi_stream_open(vm0, stream=0, csi=0)
[   57.763515] [RCE] nvcsi_calc_ths_settle ths_settle 53
[   57.763516] [RCE] nvcsi_calc_ths_settle ths_settle 53
[   57.763518] [RCE] nvcsi_calc_ths_settle ths_settle 53
[   57.763519] [RCE] nvcsi_calc_tclk_settle tclk_settle 75
[   57.855527] ox01f10 10-0011: ox01f10_start_streaming ++
[   57.855538] ox01f10 10-0011: ox01f10_write_table: channel 0, 
[   57.855547] ox01f10 10-0011: ox01f10_write_table: write reg source :0x52 addr:0x40b val:0x42
[   58.911522] ox01f10 10-0011: ox01f10_write_table: write reg source :0x52 addr:0x8a0 val:0x84
[   58.931512] ox01f10 10-0011: ox01f10_start_streaming OX01F10_MODE_START_STREAM 0 ++
[   60.197833] mt7601u 1-3.3:1.0: Error: TSSI upper saturation
[   60.415527] tegra-camrtc-capture-vi tegra-capture-vi: uncorr_err: request timed out after 2500 ms
[   60.424661] tegra-camrtc-capture-vi tegra-capture-vi: err_rec: attempting to reset the capture channel
[   60.434712] (NULL device *): vi_capture_control_message: NULL VI channel received
[   60.442433] t194-nvcsi 13e40000.host1x:nvcsi@15a00000: csi5_stream_close: Error in closing stream_id=0, csi_port=0
[   60.453093] (NULL device *): vi_capture_control_message: NULL VI channel received

Any other diffs between xaiver and orin?
what should i do next?

[ShaneCCC]

Does the trace log the same?

[fengrongsu]

tracer: nop
#
# entries-in-buffer/entries-written: 128/128   #P:4
#
#                                _-----=> irqs-off
#                               / _----=> need-resched
#                              | / _---=> hardirq/softirq
#                              || / _--=> preempt-depth
#                              ||| /     delay
#           TASK-PID     CPU#  ||||   TIMESTAMP  FUNCTION
#              | |         |   ||||      |         |
        v4l2-ctl-2881    [001] ....    83.821686: tegra_channel_open: vi-output, ox01f10 10-0011
        v4l2-ctl-2881    [001] ....    83.825540: tegra_channel_set_power: ox01f10 10-0011 : 0x1
        v4l2-ctl-2881    [001] ....    83.825548: camera_common_s_power: status : 0x1
        v4l2-ctl-2881    [001] ....    83.845538: tegra_channel_set_power: 13e40000.host1x:nvcsi@15a00000- : 0x1
        v4l2-ctl-2881    [001] ....    83.845541: csi_s_power: enable : 0x1
        v4l2-ctl-2881    [001] ....    83.845927: tegra_channel_capture_setup: vnc_id 0 W 1280 H 960 fmt 10
        v4l2-ctl-2881    [001] ....    83.846548: tegra_channel_set_stream: enable : 0x1
        v4l2-ctl-2881    [001] ....    83.858907: tegra_channel_set_stream: 13e40000.host1x:nvcsi@15a00000- : 0x1
        v4l2-ctl-2881    [001] ....    83.858909: csi_s_stream: enable : 0x1
        v4l2-ctl-2881    [001] ....    83.859362: tegra_channel_set_stream: ox01f10 10-0011 : 0x1
     kworker/3:3-140     [003] ....    83.872877: rtcpu_string: tstamp:3286217283 id:0x04010000 str:"tegra_nvcsi_stream_set_config(vm0, stream=0, csi"
     kworker/3:3-140     [003] ....    83.872879: rtcpu_string: tstamp:3286217410 id:0x04010000 str:"=0)
"
     kworker/3:3-140     [003] ....    83.872886: rtcpu_string: tstamp:3286217788 id:0x04010000 str:"MIPI clock = 750000 kHz, tHS-SETTLE = 0, tCLK-SE"
     kworker/3:3-140     [003] ....    83.872887: rtcpu_string: tstamp:3286217900 id:0x04010000 str:"TTLE = 0
"
     kworker/3:3-140     [003] ....    83.872889: rtcpu_string: tstamp:3286218118 id:0x04010000 str:"===== NVCSI Stream Configuration =====
"
     kworker/3:3-140     [003] ....    83.872891: rtcpu_string: tstamp:3286218363 id:0x04010000 str:"stream_id: PP 0, csi_port: PORT A
"
     kworker/3:3-140     [003] ....    83.872893: rtcpu_string: tstamp:3286218630 id:0x04010000 str:"Brick: PHY 0, Mode: D-PHY
"
     kworker/3:3-140     [003] ....    83.872894: rtcpu_string: tstamp:3286218921 id:0x04010000 str:"Partition: CIL A, LP bypass: Enabled, Lanes: 4
"
     kworker/3:3-140     [003] ....    83.872896: rtcpu_string: tstamp:3286219107 id:0x04010000 str:"Clock information:
"
     kworker/3:3-140     [003] ....    83.872898: rtcpu_string: tstamp:3286219413 id:0x04010000 str:"MIPI clock rate: 750.00 MHz
"
     kworker/3:3-140     [003] ....    83.872900: rtcpu_string: tstamp:3286219669 id:0x04010000 str:"T_HS settle: 0, T_CLK settle: 0
"
     kworker/3:3-140     [003] ....    83.872901: rtcpu_string: tstamp:3286219901 id:0x04010000 str:"======================================
"
     kworker/3:3-140     [003] ....    83.872903: rtcpu_string: tstamp:3286221782 id:0x04010000 str:"tegra_nvcsi_stream_open(vm0, stream=0, csi=0)
"
     kworker/3:3-140     [003] ....    83.872905: rtcpu_string: tstamp:3286228731 id:0x04010000 str:"nvcsi_calc_ths_settle ths_settle 53
"
     kworker/3:3-140     [003] ....    83.872906: rtcpu_string: tstamp:3286228996 id:0x04010000 str:"nvcsi_calc_ths_settle ths_settle 53
"
     kworker/3:3-140     [003] ....    83.872908: rtcpu_string: tstamp:3286229259 id:0x04010000 str:"nvcsi_calc_ths_settle ths_settle 53
"
     kworker/3:3-140     [003] ....    83.872910: rtcpu_string: tstamp:3286229517 id:0x04010000 str:"nvcsi_calc_tclk_settle tclk_settle 75
"
     kworker/3:3-140     [003] ....    83.872912: rtcpu_vinotify_event: tstamp:3286364919 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:105146612448 data:0x719d580010000000
     kworker/3:3-140     [003] ....    83.872913: rtcpu_vinotify_event: tstamp:3286365055 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:105146618912 data:0x0000000031000001
     kworker/3:3-140     [003] ....    83.872913: rtcpu_vinotify_event: tstamp:3286365215 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:105146664800 data:0x719d550010000000
     kworker/3:3-140     [003] ....    83.872913: rtcpu_vinotify_event: tstamp:3286365348 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:105146671360 data:0x0000000031000002
 vi-output, ox01-2883    [000] ....    86.573375: tegra_channel_capture_setup: vnc_id 0 W 1280 H 960 fmt 10
     kworker/3:3-140     [003] ....    86.620868: rtcpu_vinotify_event: tstamp:3371543774 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:107873741088 data:0x719d580010000000
     kworker/3:3-140     [003] ....    86.620869: rtcpu_vinotify_event: tstamp:3371543914 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:107873783744 data:0x0000000031000001
     kworker/3:3-140     [003] ....    86.620869: rtcpu_vinotify_event: tstamp:3371544071 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:107873801376 data:0x719d550010000000
     kworker/3:3-140     [003] ....    86.620870: rtcpu_vinotify_event: tstamp:3371544202 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:107873861760 data:0x0000000031000002
 vi-output, ox01-2883    [000] ....    89.389348: tegra_channel_capture_setup: vnc_id 0 W 1280 H 960 fmt 10

Can not find useful information.

[ShaneCCC]

Add lane_polarity = “6” in the device tree for Orin NX.
You can reference to tegra234-camera-rbpcv2-imx219.dtsi for it.