When trying to pass data from an FPGA to the Orin NX SoM over PCIe, we are not able to successfully transfer as much data as we expect based on the 4 lanes of gen 4 PCIe. This data should not be using the entire bandwidth of the PCIe connection, but we believe that this is being deprioritized or the memory controller is not able to handle all of the data across all of the connections. Is there a way to ensure that we can use the entire expected bandwidth of the PCIe lanes or make sure that connection is given priority?
To ensure that you can use the entire expected bandwidth of the PCIe lanes, here are a few suggestions:
Verify PCIe Lane Configuration: Double-check that the PCIe lanes are properly configured and that the FPGA is correctly connected to the Orin NX SoM. Ensure that the lane width and speed are correctly set up.
Check Memory Controller Performance: The memory controller’s performance can impact the overall bandwidth achieved. Check the memory controller’s specifications and ensure that it can handle the amount of data you’re trying to transfer.
Prioritize PCIe Traffic: You can try prioritizing the PCIe traffic to ensure that it gets sufficient bandwidth. This might involve configuring the system’s Quality of Service (QoS) settings or using a traffic management mechanism.
Optimize Data Transfer: Optimize the data transfer mechanism to minimize overhead and maximize bandwidth utilization. This might involve using techniques like data compression, caching, or optimizing the data transfer protocol.
Monitor System Performance: Monitor the system’s performance to identify any bottlenecks or limitations. Use tools like performance counters, system logs, or debuggers to analyze the system’s behavior and identify areas for optimization.