[Orin] Why can0 and can1 lost msg together

ckt10101 · April 19, 2024, 6:30am

Hi,
I use AGX Orin 64GB with jetpack version is 5.1.2 and Linux kernel version is L4T 35.3.1.
Some of my Orin board occasionly report “some msgs lost on in Q0” on can0 and can1, which like picture blow. And no message received on userspace for almost 400ms.

Full log here:
96a8766c-866a-4fc6-b49d-417959d948ac (1).log (59.9 KB)
Since can0 and can1 reported in the meantime, I suspect it may because of cpu load or interrupt deplay problem. So I going to larger fifo size in the device tree, and chang code below.

My question: 1. Is my suspection reasonable?
2. Is my change correct? Did Orin support set rx_fifo0_payload as 128?
Thanks for you reply!
BR/Tim

KevinFFF · April 19, 2024, 7:12am

Hi ckt10101,

L4TR35.3.1 should be included in JP5.1.1.

Are you using the devkit or custom board for AGX Orin?

May I know what’s your use case for can0 and can1?
Please share the block diagram of your connection for can0 and can1.
and also the steps how you configure them.

ckt10101 · April 19, 2024, 9:55am

Hi Kervin
I use custom board for AGX Orin.
can0 is used for communicate with pmc and can1 communicate with chassis.
schematic diagram:

About configuration, I think it only about device tree. Please refer code below:

/ {
	mttcan0: mttcan@c310000 {
		 compatible = "nvidia,tegra194-mttcan";
		 reg = <0x00 0x0c310000 0x00 0x144>,
		     <0x00 0x0c311000 0x00 0x32>,
		     <0x00 0x0c312000 0x00 0x1000>;
		 reg-names = "can-regs", "glue-regs", "msg-ram";
		 interrupts = <0 40 0x04 >;
		 pll_source = "pllaon";
		 clocks = <&bpmp_clks TEGRA234_CLK_CAN1_CORE>,
			<&bpmp_clks TEGRA234_CLK_CAN1_HOST>,
			<&bpmp_clks TEGRA234_CLK_CAN1>,
			<&bpmp_clks TEGRA234_CLK_PLLAON>;
		 clock-names = "can_core", "can_host","can","pllaon";
		 resets = <&bpmp_resets TEGRA234_RESET_CAN1>;
		 reset-names = "can";
		 mram-params = <0 16 16 32 0 0 16 16 16>;
		 tx-config = <0 16 0 64>;
		 rx-config = <64 64 64>;
		 bitrates = <500 2000>;
		 /* bittimes = <bitrate tdc_dbtp brp tseg1 tseg2 sjw support_bitrate> */
		 /* support_bitrate = nominal(0x1), data(0x2) by bitwise OR */
		 bittimes = <125  0x00 0x0F 0x13 0x03 0x00 0x03>,
			<250  0x00 0x00 0xAE 0x17 0x00 0x01>,
			<250  0x00 0x07 0x13 0x03 0x00 0x02>,
			<500  0x00 0x03 0x13 0x03 0x00 0x03>,
			<1000 0x00 0x01 0x10 0x06 0x00 0x03>,
			<2000 0x00 0x00 0x10 0x06 0x00 0x02>;
		 status = "disabled";
	 };

	mttcan1: mttcan@c320000 {
		 compatible = "nvidia,tegra194-mttcan";
		 reg = <0x00 0x0c320000 0x00 0x144>,
		     <0x00 0x0c321000 0x00 0x32>,
		     <0x00 0x0c322000 0x00 0x1000>;
		 reg-names = "can-regs", "glue-regs", "msg-ram";
		 interrupts = <0 42 0x04 >;
		 pll_source = "pllaon";
		 clocks = <&bpmp_clks TEGRA234_CLK_CAN2_CORE>,
			<&bpmp_clks TEGRA234_CLK_CAN2_HOST>,
			<&bpmp_clks TEGRA234_CLK_CAN2>,
			<&bpmp_clks TEGRA234_CLK_PLLAON>;
		 clock-names = "can_core", "can_host","can","pllaon";
		 resets = <&bpmp_resets TEGRA234_RESET_CAN2>;
		 reset-names = "can";
		 mram-params = <0 16 16 32 0 0 16 16 16>;
		 tx-config = <0 16 0 64>;
		 rx-config = <64 64 64>;
		 bitrates = <500 2000>;
		 /* bittimes = <bitrate tdc_dbtp brp tseg1 tseg2 sjw support_bitrate> */
		 /* support_bitrate = nominal(0x1), data(0x2) by bitwise OR */
		 bittimes = <125  0x00 0x0F 0x13 0x03 0x00 0x03>,
			<250  0x00 0x00 0xAE 0x17 0x00 0x01>,
			<250  0x00 0x07 0x13 0x03 0x00 0x02>,
			<500  0x00 0x03 0x13 0x03 0x00 0x03>,
			<1000 0x00 0x01 0x10 0x06 0x00 0x03>,
			<2000 0x00 0x00 0x10 0x06 0x00 0x02>;
		 status = "disabled";
	 };
};

KevinFFF · April 22, 2024, 3:20am

I would like to know the block diagram(which can interface is in use? Is CAN transceiver involved? how you connect them) rather than schematic for specific part.

The configuration I mean is how you setup can interface.
You may load mttcan first and then use ip link command to configure them.
I want to know the detailed parameters you used to configure them.

ckt10101 · April 23, 2024, 11:43am

Hi Kevin,
My block diagram below:

And configuration:

4: can1: <NOARP,UP,LOWER_UP,ECHO> mtu 16 qdisc pfifo_fast state UP mode DEFAULT group default qlen 10
    link/can  promiscuity 0 minmtu 0 maxmtu 0
    can state ERROR-ACTIVE (berr-counter tx 0 rx 0) restart-ms 100
          bitrate 500000 sample-point 0.870
          tq 20 prop-seg 43 phase-seg1 43 phase-seg2 13 sjw 1
          mttcan: tseg1 2..255 tseg2 0..127 sjw 1..127 brp 1..511 brp-inc 1
          mttcan: dtseg1 1..31 dtseg2 0..15 dsjw 1..15 dbrp 1..15 dbrp-inc 1
          clock 50000000
          re-started bus-errors arbit-lost error-warn error-pass bus-off
          0          0          0          0          0          0         numtxqueues 1 numrxqueues 1 gso_max_size 65536 gso_max_segs 65535
    RX: bytes  packets  errors  dropped overrun mcast
    69274904   8659363  5       0       5       0
    TX: bytes  packets  errors  dropped carrier collsns
    16745888   3523571  0       0       0       0
3: can0: <NOARP,UP,LOWER_UP,ECHO> mtu 16 qdisc pfifo_fast state UP mode DEFAULT group default qlen 10
    link/can  promiscuity 0 minmtu 0 maxmtu 0
    can state ERROR-ACTIVE (berr-counter tx 0 rx 0) restart-ms 100
          bitrate 500000 sample-point 0.870
          tq 20 prop-seg 43 phase-seg1 43 phase-seg2 13 sjw 1
          mttcan: tseg1 2..255 tseg2 0..127 sjw 1..127 brp 1..511 brp-inc 1
          mttcan: dtseg1 1..31 dtseg2 0..15 dsjw 1..15 dbrp 1..15 dbrp-inc 1
          clock 50000000
          re-started bus-errors arbit-lost error-warn error-pass bus-off
          0          0          0          0          0          0         numtxqueues 1 numrxqueues 1 gso_max_size 65536 gso_max_segs 65535
    RX: bytes  packets  errors  dropped overrun mcast
    142775112  17846889 5       0       5       0
    TX: bytes  packets  errors  dropped carrier collsns
    0          0        0       0       0       0

ckt10101 · April 23, 2024, 11:46am

And I found when problem happen v4l2 polling will timeout, network socket will timeout in the meanwhile. And cpu load only about 60%.
BR/Tim

KevinFFF · April 24, 2024, 5:56am

There’s only CAN-TX/CAN-RX from AGX Orin and you would need CAN transceiver to transform them to CAN-H/CAN-L. Do you connect CAN transceiver in your setup?

What is VCU and PCM device?

Please share the full commands how you setup can interface from AGX Orin.

system · May 22, 2024, 2:18am

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[Orin] Why can0 and can1 lost msg together

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