NVIDIA doesn’t publicly document machine instruction to that level of detail. Check Scott Grey’s maxas (SASS assembler for Maxwell), he spent much time reverse engineering the machine instructions. Or post some actual examples here in context and we might be able to figure it out.
As was recently discussed in these forums, there appear to be eight one-bit predicate registers, one of which is the predefined predicate “true”, which is displayed as PT in disassembly. If I recall correctly, PT occupies the encoding that would designate P7 otherwise. So P0 through P6 are available to programs.