PCIe BAR disabled on Jetson TX2 using Xilinx

Robotics & Edge Computing Jetson & Embedded Systems Jetson TX2
3

Is this the only device connected to Jetson board? If so, you can make modifications to the device-tree to allocate more aperture for mapping non-prefetchable regions of endpoint

--- a/kernel-dts/tegra186-soc/tegra186-soc-base.dtsi
+++ b/kernel-dts/tegra186-soc/tegra186-soc-base.dtsi
@@ -1518,8 +1518,8 @@
                          0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000   /* port 1 configuration space */
                          0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000   /* port 2 configuration space */
                          0x81000000 0 0x0        0x0 0x50000000 0 0x00010000   /* downstream I/O (64 KiB) */
-                         0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000   /* non-prefetchable memory (127 MiB) */
-                         0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */
+                         0x82000000 0 0x50100000 0x0 0x50100000 0 0x1ff00000   /* non-prefetchable memory (512 MiB) */
+                         0xc2000000 0 0x70000000 0x0 0x70000000 0 0x10000000>; /* prefetchable memory (256 MiB) */

                status = "disabled";