The majority of our tests were done with our own PCB instead of the Jetson carrier board. That said, we still encountered interference with the GPS module from the TX1 on the Jetson. I’m trying to follow up on the exact steps we used.
The easiest test to run would be to obtain a GPS module and monitor the carrier-to-noise ratio (CNO). Our PCIe device is an Atheros card (PCIe Gen 1).
I have also attempted to update the PCIe drivers (in the R24.2 L4T release) to vary the amplitude and timing of the PCIe REFCLK, TX and RX lanes. Unfortunately, I have not managed to observe any changes when scoping the lines. Maybe you can provide some guidance and feedback. Here is what I’ve attempted so far:
- Disable spread spectrum (SS).
This was accomplished by updating the CLK_RST_CONTROLLER_PLLE_SS_CNTL_0 register to set the SSCBYP, INTERP_RESET and BYPASS_SS bits. I made sure that USE_PLLE_SS was defined to 0 in both include/linux/platform/tegra/clock.h and drivers/platform/tegra/tegra12_clocks.c.
I wasn’t able to measure any change in REFCLK after this change.
- Attempt to modify the timing parameters of the TX signal.
It looks like this could be accomplished with the T_PCIE2_RP_LINK_CONTROL_STATUS_2 register by setting the TRANSMIT_MARGIN bit. However, updating this to a value of 011b from the default did not have any noticeable changes. I would expect a significant change in the amplitude of the signal.
I tested this change both with and without modifying the CTL_TX_MARGIN_OVERRIDE bit in the T_PCIE2_RP_PRIV_XP_LCTRL_2 register.
If these aren’t the right registers, I am hoping the registers in T_PCIE2_RP_ECTL_1_R1 (section 188.8.131.52 in the TRM) will allow us to tweak the timing parameters for TX.
- Attempted to configure PCIe with -3.5dB deemphasis instead of -6dB. (Thanks to linuxdev for this suggestion.)
This was accomplished by setting the DEEMPHASIS_STRAP and ENFORCE_DEEMPHASIS bits in the T_PCIE2_RP_PRIV_XP_LCTRL_2 register.
Again, we did not notice any change in the signals. The status from the CURRENT_DEEMPHASIS_LEVEL bit in the T_PCIE2_RP_LINK_CONTROL_STATUS_2 did not seem to indicate the device was configured for 3.5dB deemphasis.