We are using a typical communication scheme between TX1 and FPGA - PCIe x4.
The whole system sleep/wake behavior is working in our system.
The problem is partial down of the FPGA to save power.
I mean we need to turn off FPGA which looks as a PCIe device for the TX1. I.e. to turn it into D3cold state.
Unfortunately our pcie-axi ip-core is not supporting any advanced power saving modes. L1 L2 link states are not available.
Any methods based on unbinging or removal PCIe drivers do not turn the PCIe link off (L3 state).
Please advise how to dynamically turn off PCIe device (link to L3, device to D3cold) and restore it back.
Does your device support ASPM L1 Sub-States (L1.1 and L1.2), if yes, based on entry into L1.1 or L1.2, majority of your FPGA circuitry can be turned off.
(you have already clarified in your initial post that your device doesn’t support L1, I’m wondering if it supports ASPM-L1SS)
We have rewritten all our PCIe related drivers taking into account some special power management states.
So, I should say, it was a hard job and finally code is almost completely different.
Now it works. It can sleep and awake, the PCIe subsystem can be put into low power mode or completely turned off taking all the rest in active states.
So, the problem was in code of our drivers. Drivers should be written with support of advanced power management states.