PCI detection problems during system booting 1

Hi all,

in the following link you have my discussion about a problem with Jetson TX2 and the pcie discovering. As summary, we develop a board which connects Jetson TX2 and FPGA Ultrascale via PCIexpress. In general, the discovering process works correctly; however, sometimes, Jetson does not detect the FPGA PCIe link, and we must reset it twice or three times until the FPGA is discovered correclty again.

Following the comments of @linuxdev, I discard problems on power-up because FPGA is fully programmed before even the processor starts the booting, and additionally, this problem happens when the TX2 is reset, and in this process, the FPGA is not reprogrammed.

I focus on PCIe reset signal, and that maybe, the FPGA PCIe core is not ready after a reset. I fixed this reset signal to ‘1’ in the FPGA side, so this core is not reset by Jetson PCIe reset signal. However, this causes an permanent error during discovering process, and link 0 is not stablished. In normal operation, link 0 is stablished, but then an error takes place.

Any suggestions?

Thanks and regards,


Make Tegra PCIe driver as a module and load it once FPGA boot up is complete done.
Tegra PCIe driver path: kernel/kernel-4.9/drivers/pci/host/pci-tegra.c


Dear @Manikanta,
thanks for your response. I verified with lsmod that PCIe driver is a module.

ubuntu@tegra-ubuntu:~$ lsmod
Module                  Size  Used by
xdma                   74590  0
spidev                  9920  0
pci_tegra              60038  0

Regarding to the booting , the power-up sequence has a similar concept with Jetson TX2 evaluation board. In our case, the FPGA done signal, which indicates a succesfull FPGA programming, release Jetson reset_out# and starting OS booting. So during power-up, we verified that the FPGA is programmed before Jetson TX2 starts the booting.

Once the board is powered, the Jetson reboots does not affect to FPGA program. Only signals can have an impact over the FPGA PCIe driver. I reviewed FPGA global reset signal (which does not affect to PCIe core), which is released when the OS is completely booted, and PCIe reset signal, which is released previous to PCIe module load in the Jetson TX2, but I didn’t find a connection with my problem.

Any ideas? Could this error be caused by the xdma module, and that the pcie module works correctly?



I don’t know about xdma you are referring here. Could you let me know what exactly you are looking from Tegra side?

In general for PCIe link up issues, I suggest below.

  1. Limit link speed to Gen1.
  2. Disable PCIe power down and check DLL active in root port(lspci -vvv).
    Apply attached patch for above two.
  3. Capture LA trace and see at what of link negotiation it failed.
    0001-DNI-disable-pcie-power-down-and-limit-to-gen1.patch (2.0 KB)


Thanks again @Manikanta,

XDMA are Xilinx PCIe DMA drivers.


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