We are designing our carrier board for agx-xavier. We would like to reverse PCIe lanes for C0 used for M.2 M key for SSD, in order to facilitate PCB layout. And we use PCIe in root-complex mode ONLY on Xavier side.
Original: UPHY2 → lane0, UPHY3 → lane1, UPHY4 → lane2, UPHY5 → lane3.
Reverse: UPHY5 → lane0, UPHY4 → lane1, UPHY3 → lane2, UPHY2 → lane3.
Please check my attached screenshot for detail.
- Is this PCIe lane reversal supported by PCIe controller on Xavier?
- Do I need any software change in Linux device-treee and/or Linux PCIe driver?
- Can I do the lane reversal on other multi-lane PCIe controllers: C4 and C5?
- Is this PCIe lane reversal independent on the PCIe endpoint/device that is connected with (work for any PCIe endpoint/device)?
- Instead of lane reversal, can I do any lane swap in random way within the PCIe controller group? For example, for my C0 case, can I do UPHY3 → lane0, and UPHY2 → lane1 (UPHY4 and PUHY5 unchanged.)? I think the answer is no, but I want to confirm on it.