I used the M.2 Key M slot to install a Samsung V-Nand SSD 970 Pro on my AGX Xavier (Developer kit, L4T release R32.2.1).
I want to move data to/from the SSD to the GPU memory through DMA. So I found this project https://github.com/enfiskutensykkel/ssd-gpu-dma that provides an API for building userspace NVMe drivers.
I tried to run it but, I seems it can’t work with SMMU enabled. So I disabled the SMMU for PCIe controller-0 with the instructions of in comment #4 of https://devtalk.nvidia.com/default/topic/1043746/jetson-agx-xavier/pcie-smmu-issue/. After reflashing the Xavier board with the new device tree, I verified that SMMU is disabled for PCIe controller-0 by extracting current device-tree.
However, when I tried to run one example of this project (https://github.com/enfiskutensykkel/ssd-gpu-dma), I got an unhandled context fault on smmu1 and new errors (from memory controller). Bellow, the output of ‘dmesg -w’:
[ 867.404231] mc-err: (255) csr_pcie0r: EMEM address decode error [ 867.404418] mc-err: status = 0x200640d8; addr = 0xffffffff00; hi_adr_reg=ff08 [ 867.404574] mc-err: secure: yes, access-type: read [ 867.404675] mc-err: mc-err: unknown intr source intstatus = 0x00000000, intstatus_1 = 0x00000000 [ 867.404702] t19x-arm-sumu: Unhandled context fault: smmu1, iova=0x398325000, fsynr=0xd0001, cb=0, sid=86(0x56 - PCIE0), pgd=0, pud=0, pmd=0, pte=0
How can I completely disable SMMU for PCIe controller-0? How can I fixe the mc-err errors?