I have a 100G Mellanox RDMA NIC (MT27800 Family [ConnectX-5]) installed for RoCE and setup lossy RoCE Accelerations according to https://community.mellanox.com/s/article/How-to-Enable-Disable-Lossy-RoCE-Accelerations
In my current setup it is possible that the network switch reorders packets within a QP that are sent to my RDMA NIC. The packets are in quick succession e.g. there is less than microsecond delay between the reordesr.
For example the following trace can happen:
RDMA Write Only (PSN: 12376722)
RDMA Read Req (PSN: 12376724) // comes in to early
RDMA Write Only (PSN: 12376723)
The NIC then replies with a CNP Packet and a NAK (PSN Error for 12376723)
Is there a way to relax these constraints on my NIC, e.g. by modifying some registers? I could do a similar thing to disable the iCRC32 validation. As of now I have no way to enforce correct ordering inside the network, therefore I look for a way such that the NIC accepts these packet traces.
Any help would be appreciated!
- Attached is a screenshot of the packet dump.
- If I’m in the wrong sub-forum, please move this topic.