I meet some problems when I enabling the SPI by modifying DTB files.
I use the methods refer to this link.https://forums.developer.nvidia.com/t/about-using-spi-on-jetson-nano/210372/21
And change all of the nodes mentioned. Like below:
spi1_mosi_pc0 {
nvidia,pins = “spi1_mosi_pc0”;
nvidia,function = “spi1”;
nvidia,pull = <0x1>;
nvidia,tristate = <0x0>;
nvidia,enable-input = <0x1>;
};
Then after rebooting, and see the tegra_pinctrl_reg file, the register information has not been changed. It looks like below:
Bank: 1 Reg: 0x70003050 Val: 0x0000e045 → spi1_mosi_pc0
Bank: 1 Reg: 0x70003054 Val: 0x0000e045 → spi1_miso_pc1
Bank: 1 Reg: 0x70003058 Val: 0x0000e045 → spi1_sck_pc2
Bank: 1 Reg: 0x7000305c Val: 0x0000e049 → spi1_cs0_pc3
Bank: 1 Reg: 0x70003060 Val: 0x0000e049 → spi1_cs1_pc4
Bank: 1 Reg: 0x70003064 Val: 0x00006046 → spi2_mosi_pb4
Bank: 1 Reg: 0x70003068 Val: 0x00006046 → spi2_miso_pb5
Bank: 1 Reg: 0x7000306c Val: 0x00006046 → spi2_sck_pb6
Bank: 1 Reg: 0x70003070 Val: 0x00006046 → spi2_cs0_pb7
Bank: 1 Reg: 0x70003074 Val: 0x00006045 → spi2_cs1_pdd0
Bank: 1 Reg: 0x70003078 Val: 0x0000e015 → spi4_mosi_pc7
Bank: 1 Reg: 0x7000307c Val: 0x0000e015 → spi4_miso_pd0
Bank: 1 Reg: 0x70003080 Val: 0x0000e015 → spi4_sck_pc5
Bank: 1 Reg: 0x70003084 Val: 0x0000e015 → spi4_cs0_pc6
Bank: 1 Reg: 0x70003088 Val: 0x00002015 → qspi_sck_pee0
Bank: 1 Reg: 0x7000308c Val: 0x00002015 → qspi_cs_n_pee1
Bank: 1 Reg: 0x70003090 Val: 0x00002015 → qspi_io0_pee2
Bank: 1 Reg: 0x70003094 Val: 0x00002015 → qspi_io1_pee3
Bank: 1 Reg: 0x70003098 Val: 0x00002015 → qspi_io2_pee4
Bank: 1 Reg: 0x7000309c Val: 0x00002015 → qspi_io3_pee5
Bank: 0 Reg: 0x70000b70 Val: 0x00000001 → drive_qspi_comp_control
Bank: 0 Reg: 0x70000b78 Val: 0x00000001 → drive_qspi_lpbk_control
Bank: 0 Reg: 0x70000a78 Val: 0x00808000 → drive_qspi_comp
According the Moderator says, Looks like my device didn’t apply well.
I don’t know why, could any handsome/beautifuy experts surport for me?
Pretty thanks!