CSI Unit: MIPI-CSI compatible input subsystem is responsible for obtaining data from the camera, organizing the pixel format and sending it to the VI unit. There are 6 pixel parser (PP) units, each of which can accept input from a single 2-lane camera. In addition to this 6-camera model, the inputs can also be reconfigured to connect three mono or stereo 4-channel cameras to PPA, CSI1_PPA, and CSI2_PPA pairs.
VI: The video input unit receives data from the CSI unit through the 24-bit bus, the location of the data is determined by the input format. This data can then be routed to any one or two of the following interested parties. VI also has a Host 1x interface with 2 channels - one for controlling I2C access to the camera and the other for VI register programming
I have some questions is as follows:
Does the above description of csi unit/vi make sense?
Is it true that VI also has a Host 1x interface with 2 channels? Because in the configuration of the device tree, I only see that nvcsi is configured under host1x
Does the above description of csi unit/vi make sense? —> Yes it’s correct.
Is it true that VI also has a Host 1x interface with 2 channels? Because in the configuration of the device tree, I only see that nvcsi is configured under host1x → it means have two VI HW logics. like below. It’s a pairs property. The first parameter is port number second is assign to which VI logic.
And I saw the following description of VI unit:
VI Unit provides a hardware-software synchronization mechanism called VI synchronization Points (syncpts) to wait for certain conditions to be met and to increase the counter or expect the counter to reach a specific value. Multiple predefined indexes are available, each corresponding to a function such as the start of a frame, the end of a line, and the completion of ISP processing. For example, the software may choose to wait until a frame is received through the VI indicated by the next counter value corresponding to the index.
I want to confirm the correctness of the above description and which part of the code has the above description？
There are two Host 1x ch0 and Host 1x ch1 next to VI module in the figure. I still don’t understand. It seems that the configuration of this block is not involved in the device tree？
