In my view it is generally not possible to direct accesses to one of the two L2 partitions in A100. AFAIK NVIDIA does not publish documentation that describes which accesses will be directed to which partition.
Related topics
| Topic | Replies | Views | Activity | |
|---|---|---|---|---|
| How to utilize L2 partition? | 4 | 976 | January 18, 2023 | |
| Meanings of L2 --> L2 copy | 1 | 705 | January 17, 2022 | |
| Why A100 has the connection between two L2 partitions? Do they have different latency from L1 to L2? | 0 | 491 | June 29, 2021 | |
| Fermi L2 cache How fast is the L2 cache? How do I access it? | 11 | 26260 | December 2, 2011 | |
| CUDA: How do I use L2 cache in Fermi? | 3 | 5419 | June 22, 2011 | |
| Is it possible to partition l2 cache? | 2 | 56 | March 13, 2025 | |
| Are Lovelace GPU L2 caches partitioned like the Ampere ones? | 4 | 198 | September 28, 2024 | |
| Can I disable L2 caching? | 3 | 2513 | May 27, 2015 | |
| Why L1 cache hit ratio become zero on K20? | 10 | 5681 | January 17, 2013 | |
| How to optimize for cache + shared memory on Fermi? | 8 | 3072 | April 25, 2010 |