I know that with Ampere, NVIDIA GPU’s L2 cache got partitioned in two, as described in this blog article:
what about Ada Lovelace? The L2 cache has grown further. Is it still partitioned into two parts? Or has this changed (maybe into 4 partitions)?
The Ada architecture does not have a partitioned L2 like A100 and H100. Ada chips have a larger capacity L2 cache; however, it is the number of memory client request and response ports to L2 request and response ports that require the more recent 100 class chips to have partitioned L2s, not the capacity.
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Ah, so, I’m guessing GA-102 isn’t partitioned either? And the Blackwell “Hopper successor” will be?
blackwell is partitioned in the sense that the high-end blackwell datacenter GPU consists of 2 dies, and with a bit of searching you can find statements made by one of our VP’s Bryan Catanzaro about that. The technical overview doc has this to say:
This architecture is able to incorporate a significant amount of computing power by
merging two dies into a single, unified GPU. Each of the two dies are the largest die
possible within the limits of reticle size, as big as can possibly be built today. The two dies
are connected and unified with a single 10 terabyte-per-second (TB/s) chip-to-chip NVIDIA
High-Bandwidth Interface (NV-HBI), providing one fully coherent, unified GPU.
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