Instruction cache size for Ampere and Volta Arch

Accelerated Computing HPC Compilers nvc, nvc++ and nvfortran
1

Hi,

How much is the instruction cache (L0, L1 and L2) size for A100 and V100?

2

A100’s L2 is 40 MB and L1’s combined data and shared memory cache is 192 KB per SM.
V100’s L2 is 6144 KB and L1’s combined data and shared memory cache is 128 KB per SM.

For details, please see the following whitepapers:

A100

V100

3

Thank you. I think data cache and instruction cache should be separated and numbers you mention is related to data caches.