Trying to change TX2 PEX1 to USB_SS0 as second USB 3.0 port (pins H41,H42,E42,E41)

Hi All,

We believe after reviewing the Adaptation and OEM guides for the TX2 and development kit board schematics that it’s possible to have two operable USB 3.0 ports that are multiplexed from the same PCIe root hub (using USB Lane Mapping configuration #2, the default). Yet, we can’t seem to get the configuration quite right (only one USB 3.0 port is working).

On the dev kit carrier board, pin #s F43,F44,C43,C44 are enabled by default and used by the singular USB 3.0 Type A port (J19). However, it looks as though pin #s H41,H42,E41,E42 could also be used as a separately muxed USB 3.0 port. On the development kit carrier board these pins are connected to the M.2 E-key slot as a PCIe 1X interface (PEX1). On the Auvidea J120 (IMU/MUC rev8) carrier board they are connected to a second USB 3.0 Type A port (the dreaded bottom port).

  1. Is it possible to have two operable USB 3.0 ports using the two different pin sets above and some configuration of the PEX multiplexor?
  2. Has anyone ever succeeded in getting both USB 3.0 ports of the Auvidea J120 carrier to work? In their most recent firmware modification it doesn’t appear that the second port’s USB 3.0 interface is working (but USB 2.0 via USB2 on pins B42,B43 works just fine).

For reference, it looks like in Auvidea’s device tree modifications (Auvidea firmware v1.6) they have disabled the multiplexor “pcie_lane2_mux” like so:

pcie0_lane2_mux {
            gpio-hog;
            gpios = <TEGRA_MAIN_GPIO(R, 3) 0>;
            output-low;
            label = "pcie-lane2-mux";
            status = "disabled";
        };

I can only help you from nvidia point of view. If you need help on Auvidea board, please contact them.

First, USB3.0 and M.2 key E slot on devkit are sharing the same pin. That is, if you enable the PCIe on M.2 key E slot, your USB3.0(J19) would be disabled.

Second, the multiplexor “pcie_lane2_mux” is just for choosing the mapping between USB3.0 and M.2 slot.

Thus, if you want to enable two usb3.0 port on TX2, you must make your own carrier board and may need to use config #3 or config #6.

If Auvidea board has two USB3.0 port, it indicates they are using config #3 or 6.

Hi Wayne,

Thank you for your reply! We didn’t previously understand that only one can be in use at a time.

As a followup question, is there any way, in config #2, to utilize pins H41,H42,E41, and E42 as a single USB 3.0 Type A port (at the expense of existing port, J19, which would be disabled)? In other words, can the MUX be activated using the method described in the adaptation guide, and if so, would any other changes to required to XHCI, pinctrl, or pinmux nodes to use the alternate set of pins as a USB port?

Re Auvidea, we’ve made repeated attempts to contact any representative in any department about this issue via several emails, phone (their published number in Germany is a fax machine), and multiple support tickets with no luck after a week. Given that the TX2 forum is littered with similar requests for support directly or indirectly related to their carrier boards and that they don’t, in several cases, follow the OEM guide’s best practices for third party carrier board implementation why are they still listed as an Nvidia integration and services provider on Nvidia’s site?

rknopf,

I believe all necessary changes/instructions are included in the TX2 adaptation guide and this external wiki.

https://elinux.org/Jetson/TX2_USB -> usb lane mapping.

If you apply below patch, you can route usb3-0 to H41,H42,E41,E42. And J19 is disabled as Wayne said.

pcie0_lane2_mux {
     gpio-hog;
     gpios = <TEGRA_MAIN_GPIO(R, 3) 0>;
     output-low;
     label = "pcie-lane2-mux";
 -    status = "disabled";
 +    status = "okay"; };