UART RX interrupt delay

Hello, I’m using TX2i’s UART3 with 4Mb/s baudrate, I enabled the RX’s DMA and using flow-control (RTS/CTS).
I also use 2 stop bits as advised.
I am using an oscilloscope and experiencing weird behavior.
I see that the RTS line is set for 1 bit at the beginning of a byte, once every 8 bytes (which is normal, since, to my understanding, 8 bytes is the default DMA trigger level).
Since the information I receive is not divisible by 8 (I have 6 bytes spare per information packet), I see the RTS line being set for a longer period of time few bytes time after the end of the packet.
I can explain this behavior as well, to be the timeout interrupt, where the driver copies the spare data to the tty.
So far everything is good, but once in a while, I see that a packet ends, yet there is no setting of the RTS (like the handling of the timeout interrupt is “missed”).
The next packet begins, I see that the RTS is set after 2 bytes only, like it is completing the 6 bytes “left behind” from the previous packet.
Then, a few bytes later (like 30-40), I see a long set of the RTS in the middle of a 8 bytes dma cycle.
This looks like the delayed timeout missed at the end of the previous packet.
Any idea why this happens?

hello linus.s.gates,

you might check if there’s chance of bit errors,
could you please also refer to these two forum topic threads for reference, Topic 154947 and, Topic 154707.

I looked at both topics, by problem is different, I see no data lost at all, which is also normal from what I see in the oscilloscope. Again, most of the time everything is ok, but once in a while it looks like the timeout interrupt is handled in delay, in the middle of the next information packet.
The micro-controller that sends the data reacts correctly to the RTS when it is set, so no data errors are experienced.
I’m still wondering what is the cause of this phenomena.

hello linus.s.gates,

could you please also have a check with having getty on background,
for example,
$ sudo /sbin/getty -a ubuntu -L 115200 ttyTHS<port> &