Hi Nvidia Team,
We are currently encountering persistent flashing failures on our Jetson AGX Thor DevKit. Command used for flashing is sudo ./tools/kernel_flash/l4t_initrd_flash.sh --external-device nvme0n1p1 -c tools/kernel_flash/flash_l4t_t234_nvme.xml --showlogs --network usb0 jetson-agx-thor-devkit external
Attached the complete error logs.
error.txt (115.3 KB)
Can you please help us resolve this error.
Regards,
Vrushti
Unless this is typo, might be the problem.
Orin = t234
tools/kernel_flash/flash_l4t_t234_nvme.xml
Thor = t264
tools/kernel_flash/flash_l4t_t264_nvme.xml
On your x86_64/amd64 host if it is Ubuntu run:
sudo tools/l4t_flash_prerequisites.sh
sudo ./l4t_initrd_flash.sh --external-device nvme0n1p1 \
-c ./tools/kernel_flash/flash_l4t_t264_nvme.xml \
--showlogs --network usb0 jetson-agx-thor-devkit internal
edit: but looking at your log everything is t264 so maybe that is just a typo. Is this custom board? If so does it have an eeprom?
If the carrier board is designed without an EEPROM, the following modifications are needed on the MB2 BCT file, Linux_for_Tegra/bootloader/generic/BCT/tegra264-mb2-bct-common.dtsi:
- cvb_eeprom_read_size = <0x100>
+ cvb_eeprom_read_size = <0x0>
In the board configuration file, add the following line:
+ SKIP_EEPROM_CHECK=1
We have made changes in dts which is specific to custom board, but we are booting the thor-devkit currently.
Regarding EEPROM, the carrier board will be having the eeprom
Also it was a typo from my side.
Might double check the usbc port in the linked guide to confirm.
Another distant thought would be to try increasing timeout in this file at this line.
Linux_for_Tegra/unified_flash/tools/flashtools/bootburn_t264_py/bootburn.py
updateValue = counterUpdateQueue.get(block=True, timeout=10)
I double checked, it seems the issue is not with the usb cable. I tried taking the debug serial logs but couldn’t find the rootcause.
Serial logs:
flashig_log.txt (69.8 KB)
This is might be worthwhile to run. Note: when I ran this over ssh on unmodified jetson-agx-thor-devkit and factory Jetpack 7.2 and device-tree it did not return from suspend test; so it is better to run tests not over ssh.
wget https://developer.nvidia.com/downloads/embedded/L4T/r39_Release_v2.0/release/bringup_framework_R39.2.0_aarch64.tbz2
tar xf bringup_framework_R39.2.0_aarch64.tbz2
./nv_bringup.sh --print-dependency -b jetson-agx-thor-devkit #will report if any packages need to be install to run tests.
nv_bringup.sh - Use: nv_bringup.sh [--help|-h] [-m|--module "MODULE_NAME MODULE_NAME"] [-d|--print-dependency] <-b|--board> <BOARD_NAME>
This script validates common baseline functionality on a the host board
Options are:
--help|-h
show this help
--module|-m
space separated list of modules to test (i.e. \"pcie cpu gpu\")
--print-dependency|-d
list pre-req dependencies of tests
--board|-b
name of the target board to test (i.e. jetson-agx-thor-devkit)
Hi @whitesscott ,
I am not running test over ssh, the attach logs are the debug serial logs. The device is not coming up due to following error
��Unhandled Exception in EL3.
x30 = 0x000000000ff411f4
x0 = 0x0000000000000000
x1 = 0x00000000be000011
x2 = 0x0000000000000011
x3 = 0x0000000000000000
x4 = 0x0000000000000000
x5 = 0x000000000ff96bc0
x6 = 0xffffffffffffffd8
x7 = 0x00000081200b0000
x8 = 0x0000000001000000
x9 = 0x000000000ff78000
x10 = 0x55aaababd9a453f5
x11 = 0x55aaadae668eb591
x12 = 0x0000000000000000
x13 = 0x000000000ff96788
x14 = 0x00000081200b1000
x15 = 0x0000000000000000
x16 = 0x0000001f76767340
x17 = 0xc5c6b07ef8000cdf
x18 = 0x0000001f76770100
x19 = 0x000000000ff793f0
x20 = 0x0000000000000000
x21 = 0x0000000000000000
x22 = 0x0000000000000000
x23 = 0x0000000000000000
x24 = 0x0000000000000000
x25 = 0x0000000000000000
x26 = 0x0000000000000000
x27 = 0x0000000000000000
x28 = 0x0000000000000000
x29 = 0x0000000000000000
scr_el3 = 0x000000401c07073d
sctlr_el3 = 0x00000000b0cd183f
cptr_el3 = 0x0000000000000100
tcr_el3 = 0x0000000080853510
daif = 0x00000000000002c0
mair_el3 = 0x00000000004404ff
spsr_el3 = 0x00000000420003c9
elr_el3 = 0x0000001f7676ba80
ttbr0_el3 = 0x000000000ff99001
esr_el3 = 0x00000000be000011
far_el3 = 0xdfcfdad9aac47fb8
spsr_el1 = 0x0000000000000000
elr_el1 = 0x0000000000000000
spsr_abt = 0x0000000000000000
spsr_und = 0x0000000000000000
spsr_irq = 0x0000000000000000
spsr_fiq = 0x0000000000000000
sctlr_el1 = 0x0000000030d00980
actlr_el1 = 0x0000000000000000
cpacr_el1 = 0x0000000000300000
csselr_el1 = 0x0000000000000000
sp_el1 = 0x0000000000000000
esr_el1 = 0x0000000000000000
ttbr0_el1 = 0x0000000000000000
ttbr1_el1 = 0x0000000000000000
mair_el1 = 0x0000000000000000
amair_el1 = 0x0000000000000000
tcr_el1 = 0x0000000000000000
tpidr_el1 = 0x0000000000000000
tpidr_el0 = 0x0000000080000000
tpidrro_el0 = 0x0000000000000000
par_el1 = 0x0000000000000800
mpidr_el1 = 0x0000000081000000
afsr0_el1 = 0x0000000000000000
afsr1_el1 = 0x0000000000000000
contextidr_el1 = 0x0000000000000000
vbar_el1 = 0x0000000000000000
cntp_ctl_el0 = 0x0000000000000005
cntp_cval_el0 = 0x00000001b374652b
cntv_ctl_el0 = 0x0000000000000000
cntv_cval_el0 = 0x0000000000000000
cntkctl_el1 = 0x0000000000000000
sp_el0 = 0x0000001f76770100
isr_el1 = 0x0000000000000040
cpuectlr_el1 = 0xc0007403c0543001
gicd_ispendr regs (Offsets 0x200 - 0x278)
Offset: value
0000000000000200: 0x0000000000000000
0000000000000204: 0x0000000000000000
0000000000000208: 0x0000000000000000
000000000000020c: 0x0000000000000008
0000000000000210: 0x0000000010000000
0000000000000214: 0x0000000000000000
0000000000000218: 0x0000000000000000
000000000000021c: 0x0000000000000000
0000000000000220: 0x0000000000000000
0000000000000224: 0x0000000000000000
0000000000000228: 0x0000000000000000
000000000000022c: 0x0000000000000000
0000000000000230: 0x0000000000000000
0000000000000234: 0x0000000000000000
0000000000000238: 0x0000000080000000
000000000000023c: 0x0000000000000000
0000000000000240: 0x0000000000000000
0000000000000244: 0x0000000000000000
0000000000000248: 0x0000000000000000
000000000000024c: 0x0000000000000000
0000000000000250: 0x0000000000001800
0000000000000254: 0x0000000000000000
0000000000000258: 0x0000000000000000
000000000000025c: 0x0000000000800000
0000000000000260: 0x0000000000000000
0000000000000264: 0x0000000000000000
0000000000000268: 0x0000000000000000
000000000000026c: 0x0000000000000000
0000000000000270: 0x0000000000000000
0000000000000274: 0x0000000000000000
0000000000000278: 0x0000000000000000
000000000000027c: 0x0000000000000000
FYI, I have made custom changes on the thor-devkit specific to our custom board
Hi @whitesscott , can you please guide me on how to resolve this flash error.
Hi,
The config is for orin; please run the commands as developer guide show
sudo ./l4t_initrd_flash.sh --erase-all jetson-agx-thor-devkit internal
Thanks
Hi @DavidDDD , i have reflashed the thor-devkit with updated command "./tools/kernel_flash/l4t_initrd_flash.sh --external-device nvme0n1p1 -c tools/kernel_flash/flash_l4t_t264_nvme.xml --showlogs --network usb0 jetson-agx-thor-devkit external" but the issue persist
Hi,
Please try below commands either
sudo ./l4t_initrd_flash.sh --erase-all jetson-agx-thor-devkit internal
Also upload the serial console log.
Thanks
Hi @DavidDDD
Tried flashing with the command "sudo ./l4t_initrd_flash.sh --erase-all jetson-agx-thor-devkit internal", observing the same error.
Attached the serial logs:
flash_log_1.txt (47.3 KB)
Hi,
Which DTB did you modify?
Are you currently able to flash successfully using the original clean BSP with the default DTB?
Thanks
Hi,
I have custom changes in main dtb for uart,spi,pwm,hdmi and for pcie updated bpmp. With original clean BSP everything is working fine.
Hi,
Please provide the patch your modified so we could reproduce and debug in our side.
Thanks
Hi @DavidDDD,
Please find the changes here,
PWM changes:
diff --git a/hardware/nvidia/t264/nv-public/tegra264.dtsi b/hardware/nvidia/t264/nv-public/tegra264.dtsi
index b90f371f5..192b3a44b 100644
--- a/hardware/nvidia/t264/nv-public/tegra264.dtsi
+++ b/hardware/nvidia/t264/nv-public/tegra264.dtsi
@@ -4372,7 +4372,7 @@
pwm2: pwm@810c5e0000 {
compatible = "nvidia,tegra264-pwm";
- status = "disabled";
+ status = "okay";
reg = <0x81 0x0c5e0000 0x0 0x10000>;
nvidia,hw-instance-id = <0x2>;
@@ -4411,7 +4411,7 @@
pwm9: pwm@810c610000 {
compatible = "nvidia,tegra264-pwm";
- status = "disabled";
+ status = "okay";
reg = <0x81 0x0c610000 0x0 0x10000>;
nvidia,hw-instance-id = <0x9>;
(END)
diff --git a/hardware/nvidia/t264/nv-public/nv-platform/tegra264-p4071-0000.dtsi b/hardware/nvidia/t264/nv-public/nv-platform/tegra264-p4071-0000.dtsi
index e1642d648..db159c606 100644
--- a/hardware/nvidia/t264/nv-public/nv-platform/tegra264-p4071-0000.dtsi
+++ b/hardware/nvidia/t264/nv-public/nv-platform/tegra264-p4071-0000.dtsi
@@ -324,9 +324,9 @@
interrupt-names = "wakeup";
};
- /* PCIe C3 is SNN on Jedha */
+ /* PCIe C3 for PCIE Switch */
pcie@a808440000 {
- status = "disabled";
+ status = "okay";
};
/* PCIe C4 is SNN on Jedha */
@@ -555,7 +555,15 @@
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
-
+/*
+ * P4071 devkit defines vdd_12v_cvb on PY.02 (GPIO61 / SNN_GPIO61) to enable
+ * the carrier 12 V buck (VDD_12V_EN). On SEGER that pin is wired to the
+ * PI7C9X3G606 PFX_FATAL_N input instead, and 12 V is sequenced by the power
+ * MCU (JETSON_CARRIER_PWR_ON). Keeping the devkit node would drive PY.02 as
+ * a regulator output and conflict with the switch fatal-error line.
+ */
+
+/*
vdd_12v_cvb: regulator-vdd-12v {
compatible = "regulator-fixed";
regulator-name = "VDD_12V";
@@ -567,7 +575,7 @@
enable-active-high;
regulator-boot-on;
};
-
+*/
vdd_5v0_hdmi_cvb: regulator-vdd-5v0-hdmi {
diff --git a/hardware/nvidia/t264/nv-public/tegra264.dtsi b/hardware/nvidia/t264/nv-public/tegra264.dtsi
index 088fd8ce2..b90f371f5 100644
--- a/hardware/nvidia/t264/nv-public/tegra264.dtsi
+++ b/hardware/nvidia/t264/nv-public/tegra264.dtsi
@@ -3566,7 +3566,7 @@
uart0: serial@c5f0000 {
compatible = "arm,sbsa-uart","arm,pl011";
- status = "disabled";
+ status = "okay";
reg = <0x0 0xc5f0000 0x0 0x10000>;
reg-io-width = <0x4>;
Hi @DavidDDD , i found out that enabling uart0 caused the flash failure, but i have mapped uart0 to uart3_rx_debug ports. In this case how to enable uart0 ?