Hi.
Could you help test this patch in UEFI?
diff --git a/Silicon/NVIDIA/Drivers/UsbPadCtlDxe/UsbPadCtlTegra194.c b/Silicon/NVIDIA/Drivers/UsbPadCtlDxe/UsbPadCtlTegra194.c
index 034ca8f..a4c20f8 100644
--- a/Silicon/NVIDIA/Drivers/UsbPadCtlDxe/UsbPadCtlTegra194.c
+++ b/Silicon/NVIDIA/Drivers/UsbPadCtlDxe/UsbPadCtlTegra194.c
@@ -2,7 +2,7 @@
USB Pad Control Driver Platform Specific Definitions/Functions
- Copyright (c) 2019-2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ SPDX-FileCopyrightText: Copyright (c) 2019-2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -968,6 +968,7 @@
UINT32 i, RegData;
PADCTL_PLAT_CONFIG *PlatConfig;
PORT_INFO *Usb2Ports;
+ PORT_INFO *Usb3Ports;
if (NULL == This) {
return;
@@ -976,6 +977,7 @@
Private = PADCTL_PRIVATE_DATA_FROM_THIS (This);
PlatConfig = &(Private->PlatConfig);
Usb2Ports = PlatConfig->Usb2Ports;
+ Usb3Ports = PlatConfig->Usb3Ports;
/* Disable Over Current Handling and VBUS */
DisableVbus (Private);
@@ -989,6 +991,7 @@
/* Clear Each PAD's PD and PD_DR Bits */
RegData = PadCtlRead (Private, USB2_OTG_PADX_CTL_0 (i));
RegData |= USB2_OTG_PD;
+ RegData |= USB2_OTG_PD_ZI;
PadCtlWrite (Private, USB2_OTG_PADX_CTL_0 (i), RegData);
RegData = PadCtlRead (Private, USB2_OTG_PADX_CTL_1 (i));
@@ -1005,5 +1008,28 @@
RegData |= USB2_PD_TRK;
PadCtlWrite (Private, XUSB_PADCTL_USB2_BIAS_PAD_CTL1, RegData);
+ /* Power down usb3 part */
+ for (i = 0; i < PlatConfig->NumSsPhys; i++) {
+ if (Usb3Ports[i].PortEnabled == FALSE) {
+ continue;
+ }
+
+ RegData = PadCtlRead (Private, XUSB_PADCTL_ELPG_PROGRAM_1_0);
+ RegData |= SSPX_ELPG_CLAMP_EN_EARLY (i);
+ PadCtlWrite (Private, XUSB_PADCTL_ELPG_PROGRAM_1_0, RegData);
+
+ gBS->Stall (200);
+
+ RegData = PadCtlRead (Private, XUSB_PADCTL_ELPG_PROGRAM_1_0);
+ RegData |= SSPX_ELPG_CLAMP_EN (i);
+ PadCtlWrite (Private, XUSB_PADCTL_ELPG_PROGRAM_1_0, RegData);
+
+ gBS->Stall (350);
+
+ RegData = PadCtlRead (Private, XUSB_PADCTL_ELPG_PROGRAM_1_0);
+ RegData |= SSPX_ELPG_VCORE_DOWN (i);
+ PadCtlWrite (Private, XUSB_PADCTL_ELPG_PROGRAM_1_0, RegData);
+ }
+
return;
}
diff --git a/Silicon/NVIDIA/Drivers/UsbPadCtlDxe/UsbPadCtlTegra234.c b/Silicon/NVIDIA/Drivers/UsbPadCtlDxe/UsbPadCtlTegra234.c
index c9fb059..c47036e 100644
--- a/Silicon/NVIDIA/Drivers/UsbPadCtlDxe/UsbPadCtlTegra234.c
+++ b/Silicon/NVIDIA/Drivers/UsbPadCtlDxe/UsbPadCtlTegra234.c
@@ -2,7 +2,7 @@
USB Pad Control Driver Platform Specific Definitions/Functions
- Copyright (c) 2019-2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ SPDX-FileCopyrightText: Copyright (c) 2019-2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -1113,6 +1113,7 @@
UINT32 i, RegData;
PADCTL_PLAT_CONFIG *PlatConfig;
PORT_INFO *Usb2Ports;
+ PORT_INFO *Usb3Ports;
if (NULL == This) {
return;
@@ -1121,6 +1122,7 @@
Private = PADCTL_PRIVATE_DATA_FROM_THIS (This);
PlatConfig = &(Private->PlatConfig);
Usb2Ports = PlatConfig->Usb2Ports;
+ Usb3Ports = PlatConfig->Usb3Ports;
/* Disable Over Current Handling and VBUS */
DisableVbus (Private);
@@ -1134,6 +1136,7 @@
/* Clear Each PAD's PD and PD_DR Bits */
RegData = PadCtlRead (Private, USB2_OTG_PADX_CTL_0 (i));
RegData |= USB2_OTG_PD;
+ RegData |= USB2_OTG_PD_ZI;
PadCtlWrite (Private, USB2_OTG_PADX_CTL_0 (i), RegData);
RegData = PadCtlRead (Private, USB2_OTG_PADX_CTL_1 (i));
@@ -1150,5 +1153,28 @@
RegData |= USB2_PD_TRK;
PadCtlWrite (Private, XUSB_PADCTL_USB2_BIAS_PAD_CTL1, RegData);
+ /* Power down usb3 part */
+ for (i = 0; i < PlatConfig->NumSsPhys; i++) {
+ if (Usb3Ports[i].PortEnabled == FALSE) {
+ continue;
+ }
+
+ RegData = PadCtlRead (Private, XUSB_PADCTL_ELPG_PROGRAM_1_0);
+ RegData |= SSPX_ELPG_CLAMP_EN_EARLY (i);
+ PadCtlWrite (Private, XUSB_PADCTL_ELPG_PROGRAM_1_0, RegData);
+
+ gBS->Stall (200);
+
+ RegData = PadCtlRead (Private, XUSB_PADCTL_ELPG_PROGRAM_1_0);
+ RegData |= SSPX_ELPG_CLAMP_EN (i);
+ PadCtlWrite (Private, XUSB_PADCTL_ELPG_PROGRAM_1_0, RegData);
+
+ gBS->Stall (350);
+
+ RegData = PadCtlRead (Private, XUSB_PADCTL_ELPG_PROGRAM_1_0);
+ RegData |= SSPX_ELPG_VCORE_DOWN (i);
+ PadCtlWrite (Private, XUSB_PADCTL_ELPG_PROGRAM_1_0, RegData);
+ }
+
return;
}
diff --git a/Silicon/NVIDIA/Drivers/XhciControllerDxe/XhciControllerDxe.c b/Silicon/NVIDIA/Drivers/XhciControllerDxe/XhciControllerDxe.c
index 74ca67e..c4a1110 100644
--- a/Silicon/NVIDIA/Drivers/XhciControllerDxe/XhciControllerDxe.c
+++ b/Silicon/NVIDIA/Drivers/XhciControllerDxe/XhciControllerDxe.c
@@ -2,7 +2,7 @@
XHCI Controller Driver
- Copyright (c) 2019-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ SPDX-FileCopyrightText: Copyright (c) 2019-2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -117,6 +117,9 @@
return;
}
+ /* Do UsbPadCtlDxe DeInit */
+ Private->mUsbPadCtlProtocol->DeInitHw (Private->mUsbPadCtlProtocol);
+
Status = gBS->HandleProtocol (Private->ControllerHandle, &gNVIDIAPowerGateNodeProtocolGuid, (VOID **)&PgProtocol);
if (EFI_ERROR (Status)) {
return;
diff --git a/Silicon/NVIDIA/Drivers/XusbControllerDxe/XusbControllerDxe.c b/Silicon/NVIDIA/Drivers/XusbControllerDxe/XusbControllerDxe.c
index 4f94c05..0555987 100644
--- a/Silicon/NVIDIA/Drivers/XusbControllerDxe/XusbControllerDxe.c
+++ b/Silicon/NVIDIA/Drivers/XusbControllerDxe/XusbControllerDxe.c
@@ -2,7 +2,7 @@
XUDC Driver
- Copyright (c) 2021-2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ SPDX-FileCopyrightText: Copyright (c) 2021-2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -31,7 +31,6 @@
} XUDC_CONTROLLER_PRIVATE_DATA;
NVIDIA_COMPATIBILITY_MAPPING gDeviceCompatibilityMap[] = {
- { "nvidia,tegra194-xudc", &gNVIDIANonDiscoverableXudcDeviceGuid },
{ "nvidia,tegra234-xudc", &gNVIDIANonDiscoverableXudcDeviceGuid },
{ NULL, NULL }
};