We have the problem that sometimes there is an Error -71 on our USB Hub, as seen in the dmesg output in “USB Problematik 2.txt”. This error occurs only very sporadically and not reproducible. We’re testing on a production module in a custom board.
USB Problematik 2.txt (93.9 KB)
The problem with the USB hub already exists since a previous design. First the “CYUSB3304-68LTXC” from Infineon was installed, which was replaced by a ViaLabs “VL822-Q7” due to the availability. To verify the ViaLabs USB hub in advance, we designed a test board. This was tested several times in connection with a Windows computer and various storage media. No problems were found.
The intersting thing is, when we take the original JetPack image and install it, these errors do not occur. Which is why we assume that it is probably a DTB problem:
dmesg_jetson_nano_jetpack_org.txt (75.1 KB)
Power sequencing works as described in the Product Design Guide.
„The carrier board receives the main power source and uses this to generate the enable to Jetson Nano (POWER_EN) after the carrier board has ensured the main supply is stable and the associated decoupling capacitors have charged. The carrier board supplies are not enabled at this time. Once POWER_EN is driven active (high), Jetson Nano begins to Power-ON. When the module Power-ON sequence has completed, the SYS_RESET signal is driven inactive (high) and this is used by the carrier board to enable its various supplies.“*
The 1V05 supply for the USB hub is generated from the 3V3 rail. Its DC/DC regulator is enabled as soon as the power good signal comes from the 3V3 regulator. About 5-10ms after the sys reset is pulled from the Jetson High, the 3V3 and the 1V05 are stable.
The layout of the USB is relatively unexciting. The 90R diff impedance is met and measured by the PCB manufacturer (87R according to the test report). Intrapair the traces are matched to <150µm.
Attached the Schematics from our side.
After we have measured everything electrically & have not actually changed anything in the DTB at this point, we are currently getting nowhere… Do you have an idea what it could be?
Unfortunately, we can not make a signal integrity measurement with the equipment from our side, but would exclude the layout due to the many boards and the fact that it works in the JetPack Orginal DTB.
Thank you and best regards,